Clock domain crossing synchronization circuits and methods to guarantee proper data signal order

A clock domain crossing synchronization circuit, comprising:

• a destination current buffer generating circuit in a destination clock domain, the destination current buffer generating circuit configured to generate a destination domain current buffer signal having a value indicating whether a first data buffer or a second data buffer is a current buffer to be utilized in a current data transfer cycle;
• a first synchronization circuit configured to receive the destination current buffer signal and to generate a corresponding synchronized destination current buffer signal in a source clock domain;
• a source current buffer generating circuit configured to generate a source domain current buffer signal based on the corresponding synchronized destination current buffer signal, wherein the source domain current buffer signal has a value indicating the current buffer;
• a source data transfer request generating circuit configured to receive the source domain current buffer signal to generate a source data transfer request signal in the source clock domain based on the source domain current buffer signal, the generated source data transfer request signal being associated with the current buffer indicated by the source domain current buffer signal;
• a second synchronization circuit configured to receive the source data transfer request signal and to generate a corresponding synchronized destination data transfer request signal in the destination clock domain;
• and
• a destination data transfer request and delay generating circuit in the destination clock domain and configured to receive the synchronized source data transfer request signal and the destination domain current buffer signal, the destination data transfer request and delay generating circuit configured to delay the transfer of data between a memory in the destination clock domain and the current buffer to a subsequent data transfer cycle when the current buffer indicated by a destination domain data transfer request signal does not correspond to the current buffer indicated by the destination domain current buffer signal.

An electronic system, comprising:

• a first in, first out (FIFO) memory in a destination clock domain;
• a double buffer including a first data buffer and a second data buffer in a source clock domain;
• and
• a clock domain crossing synchronization circuit, including:
• a destination current buffer generating circuit in the destination clock domain, the destination current buffer generating circuit configured to generate a destination domain current buffer signal having a value indicating either the first data buffer or the second data buffer is the current buffer to be utilized in a current data transfer cycle;
• a first synchronization circuit configured to receive the destination current buffer signal and to generate a synchronized destination current buffer signal in the source clock domain;
• a source current buffer generating circuit in the source clock domain, the source current buffer generating circuit configured to generate a source domain current buffer signal based on the synchronized destination current buffer signal, where the source domain current buffer signal has a first value indicating the first data buffer and a second value indicating to the second data buffer;
• a source data transfer request generating circuit configured to receive the source domain current buffer signal to generate a source data transfer request signal in the source clock domain based on the source domain current buffer signal, the generated source data transfer request signal being associated with the one of the first data buffer or second data buffer corresponding to the value of the source domain current buffer signal;
• a second synchronization circuit configured to receive the source data transfer request signal and to generate a synchronized destination domain data transfer request signal in the destination clock domain;
• and
• a destination data transfer request and delay generating circuit in the destination clock domain and configured to receive the corresponding synchronized source data transfer request signal and the destination domain current buffer signal, the destination data transfer request and delay generating circuit configured to delay the transfer of data between a memory in the destination clock domain and the current buffer to a subsequent data transfer cycle when the current buffer indicated by the destination domain data transfer request signal does not correspond to the current buffer indicated by the destination domain current buffer signal.