System and method for generating clock pulses for at-speed testing of integrated circuits

A method for controlling an at-speed testing of an integrated circuit (IC), the method comprising:

• receiving, by a recording circuit of the IC during the capture phase, a test clock signal from a test circuit;
• recording, by the recording circuit, a number of clock pulses of the test clock signal at a first frequency, the number used to generate an at-speed clock during the capture phase of the at-speed testing of the IC, the recording comprising counting the number of clock pulses;
• generating, by the recording circuit during the capture phase, configuration data indicative of the recorded number of clock pulses of the test clock signal;
• receiving, by a clocking system of the IC during the capture phase, a reference clock signal and the configuration data;
• extracting, by the clocking system during the capture phase, a plurality of clock pulses at a second frequency from the reference clock signal based on the configuration data;
• and
• generating, by the clocking system during the capture phase, the at-speed clock signal that comprises the extracted plurality of clock pulses, wherein a count of the plurality of clock pulses is equal to the recorded number of clock pulses of the test clock signal, and wherein the at-speed testing of the IC is enabled based on the at-speed clock signal;
• wherein a scan enable (SE) signal is provided to the clocking system and to an input of an inverter having an output coupled to an input terminal of a first flip flop of the recording circuit for recording by counting the number of clock pulses of the test clock signal, wherein the SE signal is further provided to a reset terminal of the first flip flop to reset the first flip flop during a shift phase and not to reset the first flip flop during the capture phase of the at speed testing of the IC to enable the recording, and wherein the capture phase is indicated by the SE signal being de-asserted.