Built-in self test circuit for measuring performance of clock data recovery and system-on-chip including the same

A system-on-chip comprising:

• a clock generation circuit configured to generate a first phase reference clock;
• a transmission circuit comprising a serializer configured to serialize data according to a reference clock of a first phase;
• a reception circuit comprising:
• a delay controller configured to receive the reference clock of the first phase and delay the received reference clock by a preset phase difference to generate a delay clock, and
• a Clock Data Recovery (CDR) circuit configured to receive the serialized data and generate a first recovery clock and recovery data;
• and
• a Built In Self Test (BIST) circuit comprising a CDR performance monitoring circuit configured to generate a control signal instructing generation of the delay clock and provide the control signal to the delay controller, wherein the CDR performance monitoring circuit is configured to receive a digital code from the CDR circuit and provide the control signal to the delay controller in response to a detection that the digital code is locked with a first code.

An operating method of a Built In Self Test (BIST) circuit comprises a delay controller for phase delay of a clock and a clock data recovery (CDR) performance monitoring circuit, the method comprising:

• receiving a digital code from a CDR circuit outputting a recovery clock and recovery data based on input data;
• determining whether the received digital code is locked;
• and
• delaying a phase of the input data by a predefined phase difference by providing a control signal instructing a phase delay to the delay controller in response to the determination that the digital code is locked.