Method of forming an integrated circuit via

A method, comprising:

• forming a lower metal element;
• using a first patterned photoresist to form a sacrificial element over the lower metal element;
• forming a dielectric region including a dielectric element projection extending upwardly above the sacrificial element;
• forming a second patterned photoresist including a second photoresist opening, wherein at least a portion of the dielectric element projection extends upwardly in the second photoresist opening, wherein an alignment of the second photoresist opening relative to the dielectric element projection defines an interference area between the second photoresist layer and the dielectric element projection, and wherein the second photoresist layer is physically excluded from the interference area by the dielectric element projection;
• etching a dielectric region trench opening in the dielectric region;
• removing the sacrificial element to define a via opening extending downwardly from the dielectric region trench opening;
• and
• filling the dielectric region trench opening and the via opening to define (a) an upper metal element in the dielectric region trench opening and (b) a via in the via opening, wherein the via extends downwardly from the upper metal element.

A method, comprising:

• forming a sacrificial material layer in an integrated circuit structure;
• using a bright field photomask to define a first photoresist element over the sacrificial material layer;
• etching the sacrificial material layer to form a sacrificial element below the first photoresist element,
• forming a dielectric region over the sacrificial material layer, the dielectric region including a dielectric element projection extending upwardly above the sacrificial element;
• forming a second patterned photoresist including a second photoresist opening, wherein at least a portion of the dielectric element projection extends upwardly in the second photoresist opening wherein an alignment of the second photoresist opening relative to the dielectric element projection defines an interference area between the second photoresist layer and the dielectric element projection, and wherein the second photoresist layer is physically excluded from the interference area by the dielectric element projection;
• etching through the second photoresist opening to form a dielectric region trench opening in the dielectric region, the dielectric region trench opening exposing a portion of a surface of the sacrificial element;
• removing the sacrificial element to define a via opening;
• and
• filling the dielectric region trench opening and the via opening to define (a) an upper metal element in the dielectric region trench opening and (b) a via in the via opening.

An integrated circuit device formed by a process including:

• depositing a sacrificial material layer over an integrated circuit structure;
• forming a first photoresist layer over the sacrificial material layer;
• patterning the first photoresist layer to define a first photoresist element;
• etching the sacrificial material layer to form a sacrificial element below the first photoresist element;
• depositing a dielectric region including a dielectric element projection extending upwardly above the sacrificial element;
• forming a second photoresist layer;
• patterning the second photoresist layer to form a second photoresist opening in the second photoresist layer, wherein at least a portion of the dielectric element projection extends upwardly in the second photoresist opening, wherein an alignment of the second photoresist opening relative to the dielectric element projection defines an interference area between the second photoresist layer and the dielectric element projection, and wherein the second photoresist layer is physically excluded from the interference area by the dielectric element projection;
• etching through the second photoresist opening to form a dielectric region trench opening in the dielectric region;
• removing the sacrificial element to define a via opening extending below the dielectric region trench opening;
• and
• filling the dielectric region trench opening and the via opening to define (a) a metal element in the dielectric region trench opening and (b) a via in the via opening, wherein the via extends downwardly from the metal element.