Wet etching process for manufacturing semiconductor structure

A method for manufacturing a semiconductor structure, comprising:

• forming a plurality of semiconductor stack portions on a semiconductor substrate, the semiconductor stack portions being spaced apart from each other by a plurality of first recesses in a first direction parallel to a surface of the semiconductor substrate, each of the semiconductor stack portions including two sacrificial layer portions and a channel layer portion disposed between the sacrificial layer portions in a second direction transverse to the first direction, the channel layer portion having a plurality of crystal planes and being formed with a straight lateral surface which extends in the second direction and which is aligned with one of the crystal planes that has a lowest etching rate for an etchant to be used for laterally etching the channel layer portion among those of the crystal planes of the channel layer portion which are able to expose to the first recesses, the channel layer portion having a first dimension in the first direction that is the same along the second direction;
• forming two inner spacers, each of which laterally covers a corresponding one of the sacrificial layer portions such that the inner spacers are separated from each other by the channel layer portion;
• and
• laterally etching the channel layer portion using the etchant to form a second recess between the two inner spacers such that the channel layer portion has a second dimension in the first direction, the second dimension being smaller than the first dimension and being the same along the second direction.

A method for manufacturing a semiconductor structure, comprising:

• forming a semiconductor stack on a semiconductor substrate, the semiconductor stack including two sacrificial layers and a channel layer disposed between the sacrificial layers;
• forming a patterned mask on the semiconductor stack, the patterned mask including a plurality of mask portions spaced apart from each other in a first direction parallel to a surface of the semiconductor substrate;
• forming a plurality of spacers, such that each of the mask portions is laterally covered by two corresponding ones of the spacers to form a plurality of first recesses spaced apart from each other in the first direction;
• patterning the semiconductor stack by an etching process through the first recesses so as to permit the first recesses to extend downwardly to form a plurality of semiconductor stack portions spaced apart from each other by the first recesses in the first direction, each of the semiconductor stack portions including two sacrificial layer portions and a channel layer portion disposed between the sacrificial layer portions in a second direction transverse to the first direction, the channel layer portion having a plurality of crystal planes and being formed with a first straight lateral surface which extends in the second direction and which is aligned with one of the crystal planes that has a lowest etching rate for an etchant to be used for laterally etching the channel layer portion among those of the crystal planes of the channel layer portion which are able to expose to the first recesses;
• forming two inner spacers, each of which laterally covers a corresponding one of the sacrificial layer portions such that the inner spacers are separated from each other by the channel layer portion;
• and
• laterally etching the channel layer portion using the etchant to form a second recess between the two inner spacers and to permit the channel layer portion to be formed with a second straight lateral surface facing the second recess and extending in the second direction.