Diffusion barrier to mitigate direct-shortage leakage in conductive bridging ram (CBRAM)
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChia-Wen Zhong, Yen-Liang Lin, Yao-Wen Chang
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Abstract
The present disclosure relates an integrated chip structure. The integrated chip structure includes a bottom electrode disposed within a dielectric structure over a substrate. A top electrode is disposed within the dielectric structure over the bottom electrode. A switching layer and an ion source layer are between the bottom electrode and the top electrode. A barrier structure is between the bottom electrode and the top electrode. The barrier structure includes a metal nitride configured to mitigate a thermal diffusion of metal during a high temperature fabrication process.
Claims20
A method of forming an integrated chip structure, comprising:
- forming a lower interconnect within a lower inter-level dielectric (ILD) structure over a substrate;
- forming a conductive bridging random access memory (CBRAM) stack on the lower ILD structure and the lower interconnect;
- patterning the CBRAM stack according to a mask to define a CBRAM device comprising a switching layer and an ion source layer between a first electrode and a second electrode, wherein a barrier structure is also disposed between the first electrode and the second electrode;
- forming an upper interconnect within an upper ILD structure over the CBRAM device, the upper interconnect coupled to the second electrode;
- and
- wherein the barrier structure is a same material continuously extending between a topmost surface contacting the ion source layer and a bottommost surface contacting the switching layer and wherein the barrier structure has a profile of nitrogen atomic percentage that varies as a continuous function between the bottommost surface and the topmost surface of the barrier structure.
A method of forming an integrated chip structure, comprising:
- forming a bottom electrode layer over a substrate;
- forming an intermediate switching layer over the bottom electrode layer;
- forming an intermediate barrier structure over the intermediate switching layer, wherein the intermediate barrier structure comprises a metal nitride;
- forming an intermediate ion source layer over the intermediate barrier structure;
- forming a top electrode layer over the intermediate ion source layer;
- patterning the top electrode layer, the intermediate ion source layer, the intermediate barrier structure, the intermediate switching layer, and the bottom electrode layer to form a memory device;
- and
- wherein the intermediate barrier structure has a profile of nitrogen atomic percentage that increases from a first non-zero percentage to a peak of a second percentage and decreases to a third non-zero percentage lower than the first non-zero percentage.
A method of forming an integrated chip structure, comprising:
- forming a bottom electrode layer over a substrate;
- forming an intermediate switching layer over the bottom electrode layer;
- forming an intermediate barrier structure over the bottom electrode layer, wherein the intermediate barrier structure comprises a metal having a gradient nitrogen content;
- forming an intermediate ion source layer over the bottom electrode layer, wherein the intermediate barrier structure separates the intermediate ion source layer from the intermediate switching layer;
- forming a top electrode layer over the intermediate barrier structure, the intermediate ion source layer, and the intermediate switching layer;
- patterning the top electrode layer, the intermediate barrier structure, the intermediate ion source layer, the intermediate switching layer, and the bottom electrode layer;
- and
- wherein the intermediate barrier structure has a first non-zero atomic percentage of nitrogen that is greater than 50% and the intermediate ion source layer has a second non-zero atomic percentage of nitrogen that is less than 20%.
Dependencies are inferred from the claim text.