Semiconductor device and method of fabricating a semiconductor device
AssigneeInfineon Technologies Austria AG
InventorsHarsh Naik, Timothy Henson, Ashita Mirchandani, Robert Haase, Honghai He
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Abstract
In an embodiment, a semiconductor device is provided that includes: a vertical power FET configured to switch a load current and provide a channel of a first conductivity type; and a lateral FET configured to drive the vertical power FET and provide a channel of a second conductivity type opposing the first conductivity type. The vertical power FET and the lateral FET are monolithically integrated into a semiconductor substrate of the first conductivity type and a drain of the lateral FET is electrically coupled to a gate of the vertical power FET.
Claims15
A semiconductor device, comprising:
- a vertical power FET configured to switch a load current and provide a channel of a first conductivity type;
- and
- a lateral FET configured to drive the vertical power FET and provide a channel of a second conductivity type opposing the first conductivity type;
- wherein the vertical power FET and the lateral FET are monolithically integrated into a semiconductor substrate of the first conductivity type,
- wherein a drain of the lateral FET is electrically coupled to a gate of the vertical power FET.
A method for fabricating a semiconductor device having a vertical power FET for switching a load current and a lateral FET for driving the vertical power FET, the method comprising:
- forming a plurality of trenches in a first surface of a semiconductor substrate having a first conductivity type, each trench having a base and side walls;
- forming a first insulating layer that lines the base and the side walls of the trenches;
- in a first subset of the plurality of trenches that are located in a pre-defined area of the semiconductor substrate for forming a lateral FET comprising a channel region of a second conductivity type opposing the first conductivity type, removing the first insulating layer from the base of the first subset of trenches and forming a gate insulating layer on the base of the first subset of trenches;
- inserting conductive material into the plurality of trenches;
- removing the conductive material from an upper portion of the plurality of trenches and forming a gate electrode in the first subset of trenches and a field plate in a second subset of the plurality of trenches for forming the vertical power FET comprising a channel region of the first conductivity type, wherein the second subset of trenches is arranged outside of the pre-defined area and in a switching area of the semiconductor substrate.
Dependencies are inferred from the claim text.