Semiconductor device including 2D material layers

A semiconductor device, comprising:

• a substrate;
• channels on the substrate, the channels being spaced apart from each other in a vertical direction substantially perpendicular to an upper surface of the substrate;
• a lower first gate insulation pattern contacting a lower side of each of the channels;
• an upper first gate insulation pattern contacting an upper side of each of the channels;
• a first contact layer contacting each of the channels, contacting the upper first gate insulation pattern, and contacting the lower first gate insulation pattern;
• a gate electrode on the substrate, the gate electrode surrounding lower surfaces, upper surfaces, and a sidewall of a portion of each of the channels;
• and
• source/drain layers at opposite sides, respectively, of the gate electrode,
• wherein:
• each of the channels includes a semiconducting transition metal dichalcogenide (TMD), the semiconducting TMD containing a first transition metal and first chalcogen elements, the first chalcogen elements being bonded at a lower side of the first transition metal and being bonded at an upper side of the first transition metal,
• the first contact layer is disposed between each of the channels and each of the source/drain layers and includes the first transition metal,
• the upper first gate insulation patter includes silicon oxide or a metal oxide, and
• the first transition metal included in the first contact layer is bonded with silicon or a metal included in the upper first gate insulation pattern by a covalent bond or an ionic bond.

A semiconductor device, comprising:

• a substrate;
• channel structures on the substrate, the channel structures being spaced apart from each other in a vertical direction substantially perpendicular to an upper surface of the substrate, and each of the channel structures having a first length in a first direction substantially parallel to the upper surface of the substrate;
• a lower first gate insulation pattern contacting a lower surface of each of the channel structures, the lower first gate insulation pattern having the first length in the first direction;
• an upper first gate insulation pattern contacting an upper surface of each of the channel structures, the upper first gate insulation pattern having the first length in the first direction;
• a gate electrode extending in a second direction substantially parallel to the upper surface of the substrate and crossing the first direction on the substrate, the gate electrode surrounding lower and upper surfaces and opposite sidewalls in the second direction of a central portion in the first direction of each of the channel structures;
• source/drain layers at opposite sides in the first direction, respectively, of the gate electrode;
• and
• a buffer pattern between each of the channel structures and each of the source/drain layers, the buffer pattern including a semi-metal,
• wherein:
• each of the channel structures includes a first two-dimensional (2D) material layer and a second 2D material layer stacked in the vertical direction,
• the first 2D material layer includes a semiconducting transition metal dichalcogenide (TMD), the semiconducting TMD containing a first transition metal and first chalcogen elements, the first chalcogen elements being bonded at a lower side of the first transition metal and being bonded at an upper side of the first transition metal,
• the second 2D material layer includes a second transition metal and a second chalcogen element, the second chalcogen element being bonded at a lower side of the second transition metal, and
• the second transition metal included in the second 2D material layer is bonded with an element included in the upper first gate insulation pattern are bonded by a covalent bond or an ionic bond.