US 12,550,366 B2 · Rugged LDMOS with reduced NSD in source

Abstract

An integrated circuit has a P-type substrate and an N-type LDMOS transistor. The LDMOS transistor includes a boron-doped diffused well (DWELL-B) and an arsenic-doped diffused well (DWELL-As) located within the DWELL-B. A first polysilicon gate having first sidewall spacers and a second polysilicon gate having second sidewall spacers are located over opposite edges of the DWELL-B. A source/IBG region includes a first source region adjacent the first polysilicon gate, a second source region adjacent the second polysilicon gate, and an integrated back-gate (IBG) region located between the first and second source regions. The first source region and the second source region each include a lighter-doped source sub-region, the IBG region including an IBG sub-region having P-type dopants, and the source/IBG region includes a heavier-doped source sub-region.

Claims20

Dependent claims

An integrated circuit (IC), comprising:

a gate electrode over a semiconductor layer having a first conductivity type;
a drain drift region within the semiconductor layer extending from a drain region to under a first side of the gate electrode, the drain drift region and the drain region having an opposite second conductivity type and the drain region having a first dopant concentration;
and
a source region having the second conductivity type within the semiconductor layer, the source region having a first subregion extending under an opposing second side of the gate electrode and having a second dopant concentration, and a second subregion that touches the first subregion and has a third dopant concentration less than the first dopant concentration and makes a conductive connection to an electrical contact at a top surface of the source region.

1 more element

Dependencies are inferred from the claim text.

Rugged LDMOS with reduced NSD in source

Life of this patent

Rugged LDMOS with reduced NSD in source

Life of this patent

Abstract

Claims20