Method of forming transistors of different configurations
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsWei-Lun Min, Chang-Miao Liu
Life of this patent
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Abstract
The present disclosure provides semiconductor devices and methods of forming the same. A semiconductor device of the present disclosure includes a first source/drain feature and a second source/drain feature over a substrate, a plurality of channel members extending between the first source/drain feature and the second source/drain feature, a gate structure wrapping around each of the plurality of channel members, and at least one blocking feature. At least one of the plurality of channel members is isolated from the first source/drain feature and the second source/drain feature by the at least one blocking feature.
Claims20
A semiconductor device, comprising:
- a first source/drain feature and a second source/drain feature over a substrate;
- a first semiconductor nanostructure extending between the first source/drain feature and the second source/drain feature along a direction;
- and
- a gate structure wrapping around the first semiconductor nanostructure;
- and
- wherein, along the direction, the first semiconductor nanostructure is spaced apart from the first source/drain feature or the second source/drain feature by a dielectric blocking layer.
A semiconductor device, comprising:
- a substrate;
- a first transistor disposed over the substrate and comprising a first gate structure wrapping around a first number of channel members;
- a second transistor disposed over the substrate and comprising a second gate structure wrapping around a second number of channel members;
- a third transistor disposed over the substrate and comprising a third gate structure wrapping around a third number of channel members;
- and
- a fourth transistor disposed over the substrate and comprising a fourth gate structure wrapping around a fourth number of channel members,
- wherein the first number, the second number, the third number and the fourth number are identical,
- wherein the first number of channel members are sandwiched between a first source/drain feature and a second source/drain feature,
- wherein one of the second number of channel members is end-caped by first dielectric blocking layers,
- wherein two of the third number of channel members are end-capped by second dielectric blocking layers,
- wherein three of the fourth number of channel members are end-capped by third dielectric blocking layers.
A semiconductor device, comprising:
- a mesa structure over a substrate;
- a plurality of nanostructures disposed over the mesa;
- a source/drain feature disposed over the substrate and adjacent the plurality of nanostructures;
- and
- a plurality of dielectric blocking layers sandwiched between and in contact with the plurality of nano structures and the source/drain feature.
Dependencies are inferred from the claim text.