Image processing apparatus including line interleaving controller and operating method thereof

An image processing apparatus comprising:

• a first data packing circuit configured to generate first packing data by packing first line data corresponding to a first channel to a preset data size;
• a second data packing circuit configured to generate second packing data by packing second line data corresponding to a second channel to the preset data size;
• an arbitration circuit configured to receive the first packing data and the second packing data and sequentially output the first packing data and the second packing data;
• a memory configured to store the first packing data and the second packing data;
• a line index controller configured to manage a first index for a first region in the memory in which the first packing data is stored and manage a second index for a second region in the memory in which the second packing data is stored;
• a write controller configured to control a write operation of the memory;
• a read controller configured to control a read operation of the memory;
• and
• an unpacking circuit configured to generate output data by unpacking read data output from the read controller.

An operating method of an image processing apparatus including a line interleaving controller, the operating method comprising:

• generating packing data by packing line data received through each of a plurality of channels to a preset data size;
• assigning indexes respectively corresponding the plurality of channels, and writing the packing data to a memory of the line interleaving controller based on addresses included in the assigned indexes;
• reading packing data corresponding to a channel from which line data input is completed from the memory, based on indexes assigned to the channel from which the line data input is completed;
• and
• generating output data by unpacking read data read from the memory.