Slicers and temperature offset cancelation circuits for decision feedback equalizers

A temperature offset cancelation circuit comprising:

• a first transistor associated with a first temperature-dependent beta value;
• a pair of first and second resistors, wherein the first resistor is coupled to the first transistor, and wherein the pair of first and second resistors is to modify the first temperature-dependent beta value to correspond to a second temperature-dependent beta value;
• and
• a second transistor coupled to the pair of first and second resistors, the second transistor to provide a bias current.

A Universal Serial Bus (USB) Physical Layer (PHY) of a USB system, the USB PHY comprising:

• a decision feedback equalizer (DFE) comprising:
• a summer;
• and
• a slicer, the slicer comprising:
• an integrator circuit comprising a first transistor, wherein the first transistor is associated with a first temperature-dependent beta value;
• a regenerator circuit coupled to the integrator circuit;
• a temperature offset cancelation circuit coupled to the regenerator circuit, wherein the temperature offset cancelation circuit comprises:
• a second transistor associated with a second temperature-dependent beta value;
• a pair of first and second resistors, wherein the first resistor is coupled to the second transistor, and wherein the pair of the first and second resistors is to modify the second temperature-dependent beta value to correspond to the first temperature-dependent beta value of the first transistor;
• and
• a third transistor coupled to the pair of first and second resistors, the third transistor to provide a bias current for canceling a temperature offset of the first transistor.