Memory bus integrity and data encryption (IDE)

A memory module, comprising:

• multiple memory chips to store encrypted protected data and error checking and correction (ECC) data for the encrypted protected data;
• data buffers to buffer data for the multiple memory chips, with each data buffer uniquely associated with one of the multiple memory chips, the data buffers each having a link encryption engine;
• a link encryption engine for each of the multiple memory chips, the link encryption engine to receive the encrypted protected data and error checking and correction (ECC) data for the encrypted protected data from the memory chips as read data, the link encryption engine to generate link protection for transmission of the read data to a link decryption engine of a memory controller for an associated memory chip, including to generate a link integrity tag associated with the link protection;
• and
• I/O hardware to send the read data with the link protection and the link integrity tag to the memory controller;
• wherein the link encryption engine of the data buffers includes circuitry for each of the multiple memory chips to generate the link integrity tag for a specific memory chip.

A memory controller comprising:

• I/O (input/output) hardware to couple to a memory module having multiple memory chips;
• and
• a link encryption engine to generate link protection for transmission of write data to the memory chips, the write data having encrypted protected data and error checking and correction (ECC) data for the encrypted protected data, including to generate a link integrity tag associated with the link protection;
• wherein the I/O hardware is to send the write data with the link protection and the link integrity tag to the memory module;
• and
• wherein the memory module is to perform link integrity check with a link decryption engine for each of the multiple memory chips with the link integrity tag and to store the protected data and ECC data in the memory chips;
• wherein the link decryption engine for each of the multiple memory chips comprises a link decryption circuit on each of the multiple memory chips to perform the link integrity check with the link integrity tag locally for a specific memory chip.

A memory controller comprising:

• I/O (input/output) hardware to couple to a memory module having multiple memory chips;
• and
• a link decryption engine to verify link protection on read data received from the memory chips, the read data having the link protection on encrypted protected data and error checking and correction (ECC) data for the encrypted protected data generated by a link encryption engine for each of the multiple memory chips, the link decryption engine to verify the link protection with a link integrity tag associated with the link protection provided by the link encryption engine of each of the memory chips;
• wherein the link encryption engine for each of the multiple memory chips comprises a link encryption circuit on each of the multiple memory chips to generate the link integrity tag locally for a specific memory chip.