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US 12,549,328 B2Granted
Codeword synchronization method, communication device, chip, and chip system
AssigneeHuawei Technolgoies Co., Ltd.
InventorsHao Ren, Xiang He, Xinyuan Wang
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Abstract
A codeword synchronization method includes: entering a synchronization position determining state in response to a start signal; determining a synchronization position in a received data sequence in the synchronization position determining state, where the synchronization position indicates a start position of a codeword in the data sequence; entering a loss-of-lock detection state in response to determining the synchronization position; verifying, in the loss-of-lock detection state, a plurality of codewords selected based on the synchronization position; and re-entering the synchronization position determining state in response to a verification failure.
Claims31
A method comprising:
- receiving a data sequence;
- entering a synchronization position determining state in response to a start signal, wherein the synchronization position determining state comprises a first codeword verification substate;
- selecting a candidate position in the data sequence while in the synchronization position determining state;
- entering the first codeword verification substate;
- increasing, after entering the first codeword verification substate, a first count value of a first codeword counter by E, wherein E is a first integer greater than 0;
- increasing, when a first test block satisfies a verification condition and after entering the first codeword verification substate, a second count value of a first valid codeword counter by F, wherein F is a second integer greater than 0, and wherein the first test block is based on the candidate position;
- and
- determining, when the first count value is less than or equal to a first threshold and the second count value is equal to a second threshold, the candidate position as a synchronization position in the data sequence, wherein the synchronization position indicates a start position of a codeword in the data sequence.
5 more elements
A device comprising:
- a memory configured to store instructions;
- and
- one or more processors coupled to the memory and configured to execute the instructions to cause the device to:
- receive a data sequence;
- enter a synchronization position determining state in response to a start signal, wherein the synchronization position determining state comprises a first codeword verification substate;
- select a candidate position in the data sequence while in the synchronization position determining state;
- enter the first codeword verification substate;
- increase, after entering the first codeword verification substate, a first count value of a first codeword counter by E, wherein E is a first integer greater than 0;
- increase, when a first test block satisfies a verification condition and after entering the first codeword verification substate, increase a second count value of a first valid codeword counter by F, wherein F is a second integer greater than 0, and wherein the first test block is based on the candidate position;
- and
- determine, when the first count value is less than or equal to a first threshold and the second count value is equal to a second threshold, the candidate position as a synchronization position in the data sequence, wherein the synchronization position indicates a start position of a codeword in the data sequence.
8 more elements
A chip system comprising:
- a first chip configured to:
- receive a data sequence;
- enter a synchronization position determining state in response to a start signal, wherein the synchronization position determining state comprises a first codeword verification substate;
- select a candidate position in the data sequence while in the synchronization position determining state;
- enter the first codeword verification substate;
- increase, after entering the first codeword verification substate, a first count value of a first codeword counter by E, wherein E is a first integer greater than 0;
- increase, when a first test block satisfies a verification condition and after entering the first codeword verification substate, increase a second count value of a first valid codeword counter by F, wherein is a second integer greater than 0, and wherein the first test block is based on the candidate position;
- and
- determine, when the first count value is less than or equal to a first threshold and the second count value is equal to a second threshold, the candidate position as a synchronization position in the data sequence, wherein the synchronization position indicates a start position of a codeword in the data sequence;
- and
- a second chip configured to perform codeword synchronization in an alignment marker (AM) manner, wherein the first chip and the second chip are cascaded.
8 more elements
Dependencies are inferred from the claim text.