CDR lock detection based on frequency differentials
AssigneeMarvell Asia Pte Ltd
InventorsMin Wu, Davide Visani, Mehedi Hasan
Life of this patent
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Abstract
A transceiver for a network device includes clock data recovery (CDR) circuitry having a digitally controlled oscillator (DCO) and a CDR lock detector, the CDR lock detector including a frequency differential calculator coupled to a first portion of an input to the DCO and configured to determine frequency differentials between a plurality of respective pairs of present first portions of the input to the DCO and corresponding previous first portions of the input to the DCO, and to determine an average of the frequency differentials for the plurality of respective pairs, and circuitry configured to generate, based on the average, an indication of whether the CDR circuitry is locked.
Claims20
A transceiver for a network device, the transceiver including clock data recovery (CDR) circuitry having a digitally controlled oscillator (DCO) and a CDR lock detector, the CDR lock detector comprising:
- a frequency differential calculator coupled to a first portion of an input to the DCO and configured to:
- determine frequency differentials between a plurality of respective pairs of present first portions of the input to the DCO and corresponding previous first portions of the input to the DCO, and
- determine an average of the frequency differentials for the plurality of respective pairs;
- and
- circuitry configured to generate, based on the average, an indication of whether the CDR circuitry is locked.
A method for generating an indication of whether clock data recovery (CDR) circuitry of a transceiver is locked, the method comprising:
- determining, using a frequency differential calculator, frequency differentials between a plurality of respective pairs of present first portions of an input to a digitally controlled oscillator (DCO) and corresponding previous first portions of the input to the DCO;
- determining, using the frequency differential calculator, an average of the frequency differentials for the plurality of respective pairs;
- and
- generating the indication of whether the CDR circuitry is locked based on the average.
Apparatus comprising:
- a host device configured to receive deserialized data from a transceiver;
- wherein:
- the transceiver generates the deserialized data using clock data recovery (CDR) circuitry, the transceiver comprising:
- a frequency differential calculator coupled to a first portion of an input to a digitally controlled oscillator (DCO) and configured to:
- determine frequency differentials between a plurality of respective pairs of present first portions of the input to the DCO and corresponding previous first portions of the input to the DCO, and
- determine an average of the frequency differentials for the plurality of respective pairs;
- and
- circuitry configured to generate an indication of whether the CDR circuitry is locked based on the average.
Dependencies are inferred from the claim text.