PLL using a DCO period length feedback clock pulse to determine phase error and TDC gain

A phase-locked loop (PLL) comprising:

• a time-to-digital converter (TDC) coupled to receive a reference clock signal and a feedback clock signal and configured to provide a TDC output providing phase information, the phase information indicative of a phase difference between the reference clock signal and the feedback clock signal;
• a feedback divider coupled to a digitally controlled oscillator (DCO) output signal and configured to divide the DCO output signal and supply the feedback clock signal to the TDC;
• wherein the TDC output further provides gain information, the gain information indicative of a relationship between a step size of the TDC and a period of the DCO output signal;
• a delta sigma modulator to control the feedback divider and provide a quantization error;
• and
• a scaling circuit to scale the quantization error from the delta sigma modulator based on the gain information, which indicates the relationship between the step size of the TDC and the period of the DCO output signal, and the scaling circuit to provide a scaled quantization error.

An apparatus comprising:

• a digitally controlled oscillator (DCO) configured to supply a DCO output signal;
• a feedback divider coupled to the DCO output signal and configured to divide the DCO output signal and generate a feedback clock signal, the feedback clock signal having a pulse width equal to a period of the DCO output signal;
• a time-to-digital converter (TDC) coupled to receive a reference clock signal and the feedback clock signal and configured to provide phase information in a TDC output, the phase information indicative of a phase difference between the reference clock signal and the feedback clock signal;
• wherein the TDC output further provides gain information, the gain information indicative of a relationship between a step size of the TDC and a period of the DCO output signal;
• a delta sigma modulator coupled to control the feedback divider and supply a quantization error;
• and
• a scale circuit to scale the quantization error from the delta sigma modulator according to the gain information indicative of the relationship between the step size of the TDC and the period of the DCO output signal and the scale circuit to provide an adjusted quantization error.