Semiconductor integrated circuit, interface device, and memory system
AssigneeKioxia Corporation
InventorsKeisuke Kishinami, Koji Ooiwa
Life of this patent
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Abstract
A semiconductor integrated circuit includes a first circuit generating a differential third signal based on a first signal, a second circuit generating a second signal from a third signal, wherein the second circuit includes a first signal line and a second signal line for transmitting the third signal from the first circuit to the second circuit, and a third circuit including a first terminal connected to the first signal line and a second terminal connected to the second signal line. The third circuit includes first and second electrical paths with different electrical resistances, that are connected in parallel between the first terminal and the second terminal, and is controlled to switch between the first and second electrical paths.
Claims20
A semiconductor integrated circuit for converting a differential first signal having a first voltage into a second signal having a second voltage that is higher than the first voltage, the semiconductor integrated circuit comprising:
- a first circuit configured to generate a differential third signal based on the first signal;
- and
- a second circuit configured to generate the second signal from the third signal, wherein the second circuit includes a first signal line and a second signal line for transmitting the third signal from the first circuit to the second circuit;
- and
- a third circuit including a first terminal connected to the first signal line and a second terminal connected to the second signal line, wherein the third circuit includes first and second electrical paths with different electrical resistances, that are connected in parallel between the first terminal and the second terminal, and is controlled to switch between the first and second electrical paths.
An interface device comprising:
- a level shift circuit including a semiconductor integrated circuit for converting a differential first signal having a first voltage into a second signal having a second voltage that is higher than the first voltage;
- and
- a buffer receiving a signal output by the level shift circuit, wherein the semiconductor integrated circuit comprises:
- a first circuit configured to generate a differential third signal based on the first signal;
- and
- a second circuit configured to generate the second signal from the third signal, wherein the second circuit includes a first signal line and a second signal line for transmitting the third signal from the first circuit to the second circuit;
- and
- a third circuit including a first terminal connected to the first signal line and a second terminal connected to the second signal line, wherein the third circuit includes first and second electrical paths with different electrical resistances, that are connected in parallel between the first terminal and the second terminal, and is controlled to switch between the first and second electrical paths.
A memory system comprising:
- a memory controller including an interface device having a level shift circuit including a semiconductor integrated circuit for converting a differential first signal having a first voltage into a second signal having a second voltage that is higher than the first voltage, and a buffer receiving a signal output by the level shift circuit, and a control circuit configured to control the interface device;
- and
- a semiconductor storage device configured to store data transmitted from the memory controller via the interface device,
- wherein the semiconductor integrated circuit comprises:
- a first circuit configured to generate a differential third signal based on the first signal;
- and
- a second circuit configured to generate the second signal from the third signal, wherein the second circuit includes a first signal line and a second signal line for transmitting the third signal from the first circuit to the second circuit;
- and
- a third circuit including a first terminal connected to the first signal line and a second terminal connected to the second signal line, wherein the third circuit includes first and second electrical paths with different electrical resistances, that are connected in parallel between the first terminal and the second terminal, and is controlled to switch between the first and second electrical paths.
Dependencies are inferred from the claim text.