Offset voltage cancelation for a charge amplification circuit

A circuit, comprising:

• an amplifier having a first input node and a second input node and having a first output node and a second output node;
• a bias voltage node;
• a first set of switches configured, in response to assertion of a first reset signal, to couple the first and second input nodes of the amplifier to the bias voltage node and to short circuit the first and second output nodes of the amplifier together;
• a first feedback branch coupled between the first output node and the first input node of the amplifier, the first feedback branch including:
• a first capacitor;
• and
• a second capacitor having a first terminal directly connected to the first input node of the amplifier;
• a second feedback branch coupled between the second output node and the second input node of the amplifier, the second feedback branch including:
• a third capacitor;
• and
• a fourth capacitor having a first terminal directly connected to the second input node of the amplifier;
• wherein each of the first and second feedback branches further includes:
• a second set of switches intermediate the first and second input nodes of the amplifier and the first and third capacitors;
• and
• a third set of switches intermediate the first and second output nodes of the amplifier and the first, second, third and fourth capacitors;
• wherein:
• switches in the second set of switches are configured to selectively couple the first capacitor in the first feedback branch and the third capacitor in the second feedback branch to the first and second input nodes of the amplifier, respectively, in response to assertion of a second reset signal;
• and
• switches in the third set of switches are configured to selectively couple the first capacitor in the first feedback branch and the third capacitor in the second feedback branch to the first and second output nodes of the amplifier, respectively, in response to assertion of the second reset signal;
• and
• wherein the first and second reset signals are asserted during a first phase, and wherein the first reset signal is de-asserted and the second reset signal is asserted during a second phase after the first phase.