Method for simulating an electric motor

A non-transitory computer-readable storage medium having instructions stored thereon for real-time simulation of an electric circuit, wherein the instructions are executable by a computer system comprising an operator computer configured to execute a graphical modeling environment and to generate a bitstream and a real-time computer comprising at least one programmable logic device, wherein the at least one programmable logic device comprises at least one field-programmable gate array (FPGA), and wherein the instructions, when executed by the computer system, facilitate performance of the following by the computer system:

• modeling the electrical circuit in a graphical model;
• wherein the graphical model includes a first matrix routing block, a second matrix routing block, and a common matrix calculation block;
• wherein the first matrix routing block is configured to receive a first multidimensional input signal and a second multidimensional input signal, wherein the common matrix calculation block is configured to perform a first matrix operation performed on the first multidimensional input signal and the second multidimensional input signal, wherein the first matrix operation produces a first multidimensional output signal, and wherein the first matrix routing block is configured to store the first multidimensional output signal and output the first multidimensional output signal to the second matrix routing block;
• wherein the second matrix routing block is configured to receive the first multidimensional output signal and a third multidimensional input signal, wherein the common matrix calculation block is configured to perform a second matrix operation performed on the first multidimensional output signal and the third multidimensional input signal, wherein the second matrix operation produces a second multidimensional output signal, and wherein the second matrix routing block is configured to store the second multidimensional output signal and output the second multidimensional output signal;
• wherein the bitstream is generated from at least a portion of the graphical model including the first and second matrix operations;
• and
• wherein the instructions, when executed by the computer system, further facilitate performance of the following by the computer system:
• configuring the at least one FPGA based on providing the bitstream to the at least one FPGA.

A method for real-time simulation of an electric circuit using a computer system comprising an operator computer configured to execute a graphical modeling environment and to generate a bitstream and a real-time computer comprising at least one programmable logic device, wherein the at least one programmable logic device comprises at least one field-programmable gate array (FPGA), and wherein the method comprises:

• modeling, by the operator computer, the electrical circuit in a graphical model;
• wherein the graphical model includes a first matrix routing block, a second matrix routing block, and a common matrix calculation block;
• wherein the first matrix routing block is configured to receive a first multidimensional input signal and a second multidimensional input signal, wherein the common matrix calculation block is configured to perform a first matrix operation performed on the first multidimensional input signal and the second multidimensional input signal, wherein the first matrix operation produces a first multidimensional output signal, and wherein the first matrix routing block is configured to store the first multidimensional output signal and output the first multidimensional output signal to the second matrix routing block;
• wherein the second matrix routing block is configured to receive the first multidimensional output signal and a third multidimensional input signal, wherein the common matrix calculation block is configured to perform a second matrix operation performed on the first multidimensional output signal and the third multidimensional input signal, wherein the second matrix operation produces a second multidimensional output signal, and wherein the second matrix routing block is configured to store the second multidimensional output signal and output the second multidimensional output signal;
• wherein the bitstream is generated from at least a portion of the graphical model including the matrix operations;
• and
• wherein the method further comprises:
• configuring the at least one FPGA based on providing the bitstream to the at least one FPGA.