Efficient execution of atomic instructions for single instruction, multiple thread (SIMT) architectures

A method comprising:

• identifying, from a group of active threads associated with an instruction to update a shared memory, a first set of threads having a same address corresponding to the shared memory;
• selecting a first thread of the first set of threads;
• executing the instruction for the first thread using the same address to access the shared memory;
• and
• storing a Boolean value in one or more predicate registers corresponding to remaining threads of the first set of threads to prevent executing the instruction for the remaining threads until after the first thread is executed and until at least one of the remaining threads of the first set of threads is not guaranteed to fail execution of the instruction, wherein the Boolean value indicates that the remaining threads failed to execute the instruction.

A parallel processing unit (PPU) comprising one or more execution units and a shared memory, wherein the PPU is to:

• identify, from a group of active threads associated with an instruction to update the shared memory, a first set of threads having a same address corresponding to the shared memory;
• select a first thread of the first set of threads;
• execute the instruction for the first thread on the one or more execution units using the same address to access the shared memory;
• and
• store a Boolean value in one or more predicate registers corresponding to remaining threads of the first set of threads to prevent executing the instruction for the remaining threads until after the first thread is executed, wherein the Boolean value indicates that the remaining threads failed to execute the instruction.