Multi-level PHT entry swaps based on first level miss and second level hit

A computer implemented method comprising:

• storing a plurality of lines in a branch history table (BHT), each line corresponding to at least one branch instruction and containing history information specific to the at least one branch instruction;
• storing, in a first pattern history table (PHT-1) of a multi-level pattern history table, first branch data corresponding to the at least one branch instruction included in a given line of the BHT;
• storing, in a second pattern history table (PHT-2) of the multi-level pattern history table, second branch data corresponding to the at least one branch instruction included in a given line;
• storing, in a prediction update queue, at least one PUQ entry corresponding to the at least one branch instruction, the PUQ entry including a line presence bit having one of a “1” logic state or a “0” logic state;
• and
• performing a data swap between the PHT-2 and the PHT-1 based on the logic state of the line presence bit, the data swap including replacing, at the same index, the first branch data stored in the PHT-1 with the second branch data, and replacing, at the same index, the second branch data stored in the PHT-2 with the first branch data.

A computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the processor to perform operations comprising:

• storing a plurality of lines in a branch history table (BHT), each line corresponding to at least one branch instruction and containing history information specific to the at least one branch instruction;
• storing, in a first pattern history table (PHT-1) of a multi-level pattern history table, first branch data corresponding to the at least one branch instruction included in a given line of the BHT;
• storing, in a second pattern history table (PHT-2) of the multi-level pattern history table, second branch data corresponding to the at least one branch instruction included in a given line;
• storing, in a prediction update queue, at least one PUQ entry corresponding to the at least one branch instruction, the PUQ entry including a line presence bit having one of a “1” logic state or a “0” logic state;
• and
• performing a data swap between the PHT-2 and the PHT-1 based on the logic state of the line presence bit, the data swap including replacing, at the same index, the first branch data stored in the PHT-1 with the second branch data, and replacing, at the same index, the second branch data stored in the PHT-2 with the first branch data.