Return address stack with branch mispredict recovery

A computer program product embodied in a non-transitory computer readable medium for predicting addresses, the computer program product comprising code which causes one or more processors to generate semiconductor logic for:

• accessing a processor core, wherein the processor core includes a return address stack (RAS), a local cache hierarchy, and branch prediction logic, wherein the processor core is coupled to a memory system;
• sending, to a branch execution unit, a write pointer, a read pointer, and a RAS count;
• detecting one or more call instructions in an instruction stream, wherein the detecting generates a predicted return address for each of the one or more call instructions;
• pushing, on the RAS, the predicted return address for each of the one or more call instructions, wherein the pushing is directed by the write pointer;
• recognizing one or more return instructions in the instruction stream;
• updating the write pointer and the read pointer for the RAS, wherein the updating is based on a misprediction signal from the branch execution unit and wherein the updating includes manipulating the RAS count;
• popping, from the RAS, the predicted return address for each of the one or more return instructions wherein the popping is directed by the read pointer;
• and
• rolling back, by the branch execution unit, the write pointer, the read pointer, and the RAS count to a previous value.

An apparatus for predicting addresses comprising:

• a processor core coupled to a memory wherein the processor core and the memory are used to perform operations comprising:
• accessing the processor core, wherein the processor core includes a return address stack (RAS), a local cache hierarchy, and branch prediction logic, wherein the processor core is coupled to a memory system;
• sending, to a branch execution unit, a write pointer, a read pointer, and a RAS count;
• detecting one or more call instructions in an instruction stream, wherein the detecting generates a predicted return address for each of the one or more call instructions;
• pushing, on the RAS, the predicted return address for each of the one or more call instructions, wherein the pushing is directed by the write pointer;
• recognizing one or more return instructions in the instruction stream;
• updating the write pointer and the read pointer for the RAS, wherein the updating is based on a misprediction signal from the branch execution unit and wherein the updating includes manipulating the RAS count;
• popping, from the RAS, the predicted return address for each of the one or more return instructions wherein the popping is directed by the read pointer;
• and
• rolling back, by the branch execution unit, the write pointer, the read pointer, and the RAS count to a previous value.