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US 12,543,550 B2Granted
Interconnects including graphene capping and graphene barrier layers
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsShin-Yi Yang, Ming-Han Lee, Shau-Lin Shue
Life of this patent
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Abstract
A semiconductor structure includes a semiconductor substrate, a dielectric layer, a via, a first graphene layer, and a metal line. The dielectric layer is over the semiconductor substrate. The via extends through the dielectric layer. The first graphene layer extends along a top surface of the via. The metal line spans the first graphene layer. The metal line has a line width decreasing as a distance from the first graphene layer increases.
Claims20
A semiconductor structure, comprising:
- a semiconductor substrate;
- a metal via above the semiconductor substrate;
- a metal line over the metal via;
- a first graphene layer sandwiched between the metal via and the metal line;
- and
- a second graphene layer wrapping the metal line, wherein from a cross-sectional view, the second graphene layer on a top surface of the metal line has a greater lateral dimension than the first graphene layer on the metal via.
3 more elements
A semiconductor structure, comprising:
- a semiconductor substrate;
- a metal via above the semiconductor substrate;
- a barrier layer extending across the metal via;
- a metal line over the metal via;
- and
- a first graphene layer wrapping the metal line, the first graphene layer having opposite inner sidewalls respectively in contact with opposite sides of the barrier layer.
3 more elements
A semiconductor structure, comprising:
- a semiconductor substrate;
- a first dielectric layer over the semiconductor substrate;
- a via extending through the first dielectric layer;
- a first graphene layer extending along a top surface of the via;
- and
- a metal line spanning the first graphene layer, wherein the metal line has a line width decreasing as a distance from the first graphene layer increases.
3 more elements
Dependencies are inferred from the claim text.