Backside direct contact formation
AssigneeInternational Business Machines Corporation
InventorsRuilong Xie, Kisik Choi, Nicolas Jean Loubet, Theodorus E. Standaert
Life of this patent
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Abstract
A semiconductor device is provided. The semiconductor device includes source/drain (S/D) epitaxy, a gate stack adjacent to the S/D epitaxy, a semiconductor layer underlying the gate stack and including a semiconductor material surrounded by an inner spacer, an etch stop layer underlying the semiconductor layer, back trench S/D epitaxy and a self-aligned backside contact. The backside trench S/D epitaxy contacts the S/D epitaxy and is insulated from the semiconductor material by the inner spacer. The self-aligned backside contact contacts the backside trench S/D epitaxy and is insulated from the semiconductor material by the etch stop layer.
Claims20
A semiconductor device, comprising:
- source/drain (S/D) epitaxy;
- a gate stack adjacent to the S/D epitaxy;
- a semiconductor layer underlying the gate stack and comprising a semiconductor material surrounded by an inner spacer;
- an etch stop layer underlying the semiconductor layer and comprising a lowermost etch stop layer surface;
- backside trench S/D epitaxy contacting the S/D epitaxy, comprising a lowermost backside trench S/D epitaxy surface, which is coplanar with the lowermost etch stop layer surface, and being insulated from the semiconductor material by the inner spacer;
- and
- a self-aligned backside contact contacting the backside trench S/D epitaxy and being insulated from the semiconductor material by the etch stop layer.
A semiconductor device, comprising:
- first and second pillars of source/drain (S/D) epitaxy;
- gate stacks adjacent to each of the first and second pillars of the S/D epitaxy;
- a semiconductor layer underlying each of the gate stacks and comprising a semiconductor material surrounded by an inner spacer;
- an etch stop layer underlying each semiconductor layer and comprising a lowermost etch stop layer surface;
- first and second pillars of backside trench S/D epitaxy respectively contacting the first and second pillars of the S/D epitaxy, comprising a lowermost backside trench S/D epitaxy surface, which is coplanar with the lowermost etch stop layer surface, and being insulated from the corresponding semiconductor material by the corresponding inner spacer;
- and
- a self-aligned backside contact contacting the first pillar of the backside trench S/D epitaxy and being insulated from the corresponding semiconductor material by the corresponding etch stop layer.
A method of semiconductor device fabrication, comprising:
- forming additional and sacrificial semiconductor layers underlying a gate stack;
- replacing the sacrificial semiconductor layer with an etch stop layer comprising a lowermost etch stop layer surface;
- removing a semiconductor substrate underlying the etch stop layer;
- indenting a semiconductor material of the additional semiconductor layer to form an indentation;
- disposing an inner spacer in the indentation;
- forming backside trench source/drain (S/D) epitaxy contacting S/D epitaxy to which the gate stack is adjacent, comprising a lowermost backside trench S/D epitaxy surface, which is coplanar with the lowermost etch stop layer surface, and being insulated from the semiconductor material by the inner spacer;
- and
- forming a self-aligned backside contact contacting the backside trench S/D epitaxy and being insulated from the semiconductor material by the etch stop layer.
Dependencies are inferred from the claim text.