System and method for semiconductor structure
AssigneeTokyo Electron Limited
InventorsDavid Eitan Barlaz, Angelique Raley
Life of this patent
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Abstract
A method includes forming a first masking layer over a substrate, the first masking layer including a first mask line and a second mask line, heating respective top surfaces of the first mask line and the second mask line with polarized light, and forming a second masking layer over the first masking layer with an area selective deposition process. The second masking layer is thinner over a sidewall of the first mask line than over a top surface of the first mask line.
Claims20
A method for an area selective deposition process, the method comprising:
- forming a first masking layer over a substrate, the first masking layer comprising a first mask line and a second mask line, wherein a trench between the first mask line and the second mask line has a first width;
- in a plasma processing chamber, heating respective top surfaces of the first mask line and the second mask line with polarized light, wherein the first width is smaller than half a wavelength of the polarized light;
- and
- in the plasma processing chamber, forming a second masking layer over the first masking layer with an area selective deposition process, wherein the second masking layer is thinner over a sidewall of the first mask line than over a top surface of the first mask line.
A method for manufacturing a semiconductor structure, the method comprising:
- placing a substrate into a plasma processing chamber, a patterned first masking layer being over a target layer of the substrate;
- bombarding the patterned first masking layer with linearly polarized light, wherein a polarization direction of the linearly polarized light is aligned with a pattern of trenches through the patterned first masking layer;
- performing a first area selective deposition of a second masking layer over the patterned first masking layer;
- patterning the target layer using the second masking layer and the patterned first masking layer as an etching mask;
- and
- forming a pattern between remaining portions of the target layer.
A method for manufacturing a semiconductor structure, the method comprising:
- forming a first masking layer over a target layer, the target layer being over a substrate, the first masking layer comprising a first mask line and a second mask line, wherein a trench between the first mask line and the second mask line has a first width;
- placing the substrate into a plasma processing chamber;
- heating respective top surfaces of the first mask line and the second mask line with polarized light, the first width being smaller than half a wavelength of the polarized light;
- performing a first area selective deposition of a second masking layer over the first masking layer;
- patterning the target layer using the second masking layer and the first masking layer as an etching mask;
- and
- forming a pattern between remaining portions of the target layer.
Dependencies are inferred from the claim text.