Semiconductor devices

A semiconductor device comprising:

• a substrate having first and second regions and including first and second active regions respectively extending in the first and second regions in a first direction;
• a first gate structure intersecting the first active region on the first region and extending in a second direction;
• a second gate structure intersecting the second active region on the second region and extending in the second direction;
• a plurality of channel layers spaced apart from each other in a third direction, perpendicular to an upper surface of the substrate, on each of the first and second active regions and surrounded by each of the first and second gate structures;
• first source/drain regions on opposite sides adjacent to the first gate structure and electrically connected to the plurality of channel layers;
• and
• second source/drain regions on opposite sides adjacent to the second gate structure and electrically connected to the plurality of channel layers;
• wherein each of the plurality of channel layers includes first to third semiconductor layers sequentially stacked in the third direction, such that the second semiconductor layer is between the first and third semiconductor layers, and extending parallel to each other in the first and second directions,
• wherein at least one of the first to third semiconductor layers includes silicon-germanium (SiGe);
• and
• wherein the second semiconductor layer in the first region includes a material different from a material of the second semiconductor layer in the second region.

A semiconductor device comprising:

• a substrate including an active region extending in a first direction;
• a gate structure intersecting the active region on the substrate and extending in a second direction;
• a plurality of channel layers spaced apart from each other in a third direction, perpendicular to an upper surface of the substrate, on the active region and surrounded by the gate structure;
• and
• source/drain regions in recess regions of the active region, on opposite sides adjacent to the gate structure and electrically connected to the plurality of channel layers,
• wherein each of the plurality of channel layers includes first and second semiconductor layers sequentially stacked, such that the first semiconductor layer is below the second semiconductor layer,
• wherein the second semiconductor layer includes silicon-germanium (SiGe), and
• wherein side surfaces of the first and second semiconductor layers in the second direction are coplanar with each other;
• wherein each of the plurality of channel layers further includes a third semiconductor layer on the second semiconductor layer,
• wherein the second semiconductor layer is between, in the third direction, the first and third semiconductor layers, and
• wherein a content of germanium (Ge) in each of the first and third semiconductor layers is lower than a content of Ge in the second semiconductor layer.