Configurable-aggregation retimer with lane-dedicated controllers
AssigneeAstera Labs, Inc.
InventorsEnrique Musoll, Casey Morrison, Ken (Keqin) Han, Pulkit Khandelwal, Subbarao Arumilli
Life of this patent
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Abstract
Groups of signal conductors within a configurable communication system are managed by respective, dedicated media controllers implement a configurable number of independent communication channels through coordinated action so that signal conductors need not be multiplexed to/from multiple controllers and no media controllers or input/output driver circuits therein need be disabled in any configuration.
Claims23
An integrated circuit component comprising:
- a first signaling interface to be coupled to a plurality of signaling lanes;
- lane controllers dedicated to controlling communication via respective subsets of the signaling lanes, each of the lane controllers having:
- circuitry to monitor a respective stream of information received via the respective subset of the signaling lanes for predetermined control information,
- output circuitry to transmit an event-detect signal in response to detecting the predetermined control information, and
- input circuitry to receive event-detect signals transmitted by the output circuitry of each of the others of the lane controllers;
- and
- a synchronization bus that interconnects the output circuitry of each of the lane controllers to the input circuitry of each of the others of the lane controllers such that an event-detect signal transmitted by the output circuitry within any one of the lane controllers is received via the respective input circuitry within each of the others of the lane controllers.
A method of operation within an integrated circuit component having a first signaling interface coupled to a plurality of signaling lanes, lane controllers dedicated to controlling communication via respective subsets of the signaling lanes, and a synchronization bus that couples each of the lane controllers to each of the others of the lane controllers, the method comprising:
- concurrently monitoring, within all the lane controllers, respective streams of information received via the respective subsets of the signaling lanes for predetermined control information;
- outputting, from each of the lane controllers via the synchronization bus, a respective event-detect signal in response to detecting the predetermined control information within the stream of information received via the respective subset of the signaling lanes;
- receiving, within each of the lane controllers via the synchronization bus, respective event-detect signals output by all others of the lane controllers.
An integrated circuit component comprising:
- a first signaling interface to be coupled to a plurality of signaling lanes;
- lane controllers dedicated to controlling communication via respective subsets of the signaling lanes, each of the lane controllers having:
- means for monitoring a respective stream of information received via the respective subset of the signaling lanes for predetermined control information
- means for transmitting an event-detect signal in response to detecting the predetermined control information, and
- means for receiving event-detect signals transmitted by the means for transmitting within each of the others of the lane controllers;
- and
- means for interconnecting the means for transmitting within each of the lane controllers to the means for receiving within each of the others of the lane controllers such that an event-detect signal transmitted by the means for transmitting within any one of the lane controllers is received via the respective means for receiving within each of the others of the lane controllers.
Dependencies are inferred from the claim text.