Cyclic redundancy check for staircase decoding procedures

A method for wireless communications at a transmitting device, comprising:

• calculating a set of cyclic redundancy check bits to include in each information block of a set of information blocks;
• arranging each cyclic redundancy check bit of the set of cyclic redundancy check bits in a single column or a single row of an information block of the set of information blocks;
• performing a staircase encoding procedure to encode a set of information bits for each information block of the set of information blocks;
• and
• transmitting, to a receiving device, an encoded signal comprising the set of information blocks, wherein each information block of the set of information blocks comprises at least the set of encoded information bits and the set of cyclic redundancy check bits.

An apparatus for wireless communications, comprising:

• a processor;
• memory coupled with the processor;
• and
• instructions stored in the memory and executable by the processor to cause the apparatus to:
• receive, from a transmitting device, an encoded signal comprising a set of information blocks, wherein each information block of the set of information blocks comprises a set of encoded information bits and a set of cyclic redundancy check bits;
• perform a staircase decoding procedure to decode the set of encoded information bits of a selected information block that is part of a subset of the set of information blocks that is within a sliding window, the staircase decoding procedure comprising a plurality of iterations of a decoding process applied to the subset of the set of information blocks;
• perform, in between iterations of the staircase decoding procedure applied to the subset of the set of information blocks within the sliding window, a cyclic redundancy check procedure based on the set of cyclic redundancy check bits in individual ones of the subset of the set of information blocks;
• set, based on a success of the cyclic redundancy check procedure, one or more bits of an output that comprises a set of decoded information bits corresponding to the subset of the set of information blocks;
• and
• refrain from performing remaining iterations of the staircase decoding procedure in response to setting the one or more bits of the output.

An apparatus for wireless communications, comprising:

• a processor;
• memory coupled with the processor;
• and
• instructions stored in the memory and executable by the processor to cause the apparatus to:
• calculate a set of cyclic redundancy check bits to include in each information block of a set of information blocks;
• arrange each cyclic redundancy check bit of the set of cyclic redundancy check bits in a single column or a single row of an information block of the set of information blocks;
• perform a staircase encoding procedure to encode a set of information bits for each information block of the set of information blocks;
• and
• transmit, to a receiving device, an encoded signal comprising the set of information blocks, wherein each information block of the set of information blocks comprises at least the set of encoded information bits and the set of cyclic redundancy check bits.