US 12,542,563 B2 · Linearization of delay domain analog-to-digital converters

Abstract

A delay-domain analog-to-digital converter (ADC) including first and second ADCs and corresponding look-up table (LUT) memories. Control logic controls the first ADC to convert a first analog level plus a first offset to a first digital value; controls the second ADC to convert the first analog level plus a second offset to a second digital value; and computes a first difference value between the first and second digital values. The control logic further controls the first ADC to convert the first analog level minus the first offset to a third digital value; controls the second ADC to convert the first analog level plus the second offset to a fourth digital value; computes a second difference value between the third and fourth digital values; and adjusts a correction value for the first analog level in the LUT memory based on a third difference between the first and second difference values.

Claims22

Dependent claims

A method, comprising:

converting a first analog level plus a first offset to a first digital value using a first delay domain analog-to-digital converter (ADC);
converting the first analog level plus a second offset to a second digital value using a second delay domain ADC;
computing a first difference value between the first digital value and the second digital value;
converting the first analog level minus the first offset to a third digital value using the first delay domain ADC;
converting the first analog level plus the second offset to a fourth digital value using the second delay domain ADC;
computing a second difference value between the third digital value and the fourth digital value;
computing a third difference between the first and second difference values;
and
storing, in a memory associated with the first delay domain ADC, an adjustment corresponding to the first analog level and based on the third difference.

6 more elements

A circuit, comprising:

a digital-to-analog converter (DAC), having an output;
a first analog-to-digital converter (ADC) of a delay-domain type, having an input coupled to the DAC, and having an output;
a first look-up-table, having an input coupled to the output of the first ADC, and configured to store correction values for the first ADC;
a second ADC of a delay-domain type, having an input coupled to the output of the DAC, and having an output;
and
logic circuitry, configured to modify contents of the first look-up table by performing a plurality of operations comprising:
controlling the first ADC to convert a first analog level from the DAC plus a first offset to a first digital value;
controlling the second ADC to convert the first analog level plus a second offset to a second digital value;
computing a first difference value between the first digital value and the second digital value;
controlling the first ADC to convert the first analog level minus the first offset to a third digital value;
controlling the second ADC to convert the first analog level plus the second offset to a fourth digital value;
computing a second difference value between the third digital value and the fourth digital value;
computing a third difference between the first and second difference values;
and
based on the third difference, adjusting a correction value associated with the first analog level in the first look-up table.

12 more elements

An analog-to-digital converter, comprising:

a first half analog-to-digital converter (HADC) of a delay domain type;
a first look-up-table (LUT) memory associated with the first HADC, and configured to store correction values associated with a plurality of analog levels;
a second HADC of the delay domain type;
control logic configured to adjust correction values associated with the plurality of analog levels in the first LUT memory by a plurality of operations comprising, for each of the plurality of analog levels:
controlling the first HADC to convert the analog level plus a first offset to a first digital value;
controlling the second HADC to convert the analog level plus a second offset to a second digital value;
computing a first difference value between the first digital value and the second digital value;
controlling the first HADC to convert the analog level minus the first offset to a third digital value;
controlling the second HADC to convert the analog level plus the second offset to a fourth digital value;
computing a second difference value between the third digital value and the fourth digital value;
computing a third difference between the first and second difference values;
and
based on the third difference, adjusting a correction value associated with the analog level in the first LUT memory.

10 more elements

Dependencies are inferred from the claim text.

Linearization of delay domain analog-to-digital converters

Life of this patent

Linearization of delay domain analog-to-digital converters

Life of this patent

Abstract

Claims22