Circuit and method for channel randomization based on time-interleaved ADC

A circuit for channel randomization based on time-interleaved ADC, comprising:

• a channel selection module configured to output M clock reception control signals and encoded N data reception control signals according to a main clock and a generated random number, wherein M and N are positive integers, and M is greater than N;
• a multi-phase clock distribution module configured to generate N multi-phase clocks according to a sampling main clock, redistribute the multi-phase clocks according to the clock reception control signals, and output M redistributed clock signals;
• a time-interleaved ADC module configured to output M output data and a corresponding number of channel quantization completion signals according to the redistributed clock signals;
• an adjustable delay module configured to set a delay length for the data reception control signals;
• and
• a timing distribution control module connected to an output end of the adjustable delay module and an output end of the time-interleaved ADC module, respectively, and configured to control, according to delayed data reception control signals and the channel quantization completion signals, the output data to be output sequentially in chronological order.