Semiconductor system
AssigneeSK hynix Inc.
InventorKyu Dong Hwang
Life of this patent
Estimating the term…
Abstract
A semiconductor system includes a controller configured to output a command address, data, and a write clock and an inverted write clock for latching the data through a channel, configured to output the write clock and the inverted write clock having a first set level and a second set level, respectively, by incorporating information with regard to characteristics of the channel during a pre-level interval, and configured to output the write clock and the inverted write clock that periodically toggle during a toggle interval, and a semiconductor device configured to latch and store the data in synchronization with the write clock and the inverted write clock.
Claims24
A semiconductor system comprising:
- a controller configured to output a command address, data, and a write clock and an inverted write clock for latching the data through a channel, configured to output the write clock and the inverted write clock having a first set level and a second set level, respectively, by incorporating information with regard to characteristics of the channel during a pre-level interval, and configured to output the write clock and the inverted write clock that periodically toggle during a toggle interval;
- and
- a semiconductor device configured to latch and store the data in synchronization with the write clock and the inverted write clock during the toggle interval,
- wherein, the first set level is a voltage level higher than the voltage level of a ground voltage and the second set level is a voltage level lower than the voltage level of a source voltage.
A semiconductor system comprising:
- a controller configured to output a command address, data, and a write clock and an inverted write clock for latching the data through a channel, configured to output the write clock having a first set level and the inverted write clock having a second set level in response to a code signal that is input through the channel during a pre-level interval, and configured to output the write clock and the inverted write clock that periodically toggle during a toggle interval;
- and
- a semiconductor device configured to output the code signal by detecting the write clock and the inverted write clock that are input during the toggle interval and configured to latch and store the data in synchronization with the write clock and the inverted write clock,
- wherein, the first set level is a voltage level higher than the voltage level of a ground voltage and the second set level is a voltage level lower than the voltage level of a source voltage.
Dependencies are inferred from the claim text.