Signal processing and transmission in electronic circuits

An integrated circuit (IC) chip, comprising:

• a plurality of input terminals on a plurality of buses connected to the IC chip, wherein the plurality of input terminals are coupled to output terminals of an upstream neighboring chip of a plurality of chips that is series connected to the IC chip using the plurality of buses;
• a plurality of output terminals on the plurality of buses, wherein the plurality of output terminals are coupled to input terminals of a downstream neighboring chip of the plurality of chips,
• wherein the plurality of chips comprises the IC chip, the upstream neighboring chip and the downstream neighboring chip;
• wherein the plurality of IC chips are sequentially ordered by a first set of integer indices in a first transmission direction of signals on a first bus of the plurality of buses, and wherein each IC chip is operable to selectively perform a first sequence of a combining operation and an inverting operation, or a second sequence of an inverting operation and a combining operation depending on whether an integer index of the IC chip is even or odd in the first transmission direction of signals on the first bus;
• and
• a first circuit for processing signals on the first bus of the plurality of buses, the first circuit configured to:
• receive a first input signal on the first bus from the upstream neighboring chip;
• based at least on whether the integer index of the IC chip is even or odd in the first transmission direction of signals on the first bus, perform a first sequence of a combining operation and an inverting operation, or the second sequence of an inverting operation and a combing operation, a signal produced by the IC chip and the first input signal to generate a first output signal;
• and
• transmit the first output signal to the downstream neighboring chip on the first bus.

An electronic circuit comprising:

• a plurality of integrated circuit (IC) chips that are series connected using a plurality of buses, wherein an IC chip of the plurality of IC chips comprises:
• a plurality of input terminals on a plurality of buses connected to the IC chip, wherein the plurality of input terminals are coupled to output terminals of an upstream neighboring chip of a plurality of chips that is series connected to the IC chip using the plurality of buses;
• a plurality of output terminals on the plurality of buses, wherein the plurality of output terminals are coupled to input terminals of a downstream neighboring chip of the plurality of chips,
• wherein the plurality of chips comprises the IC chip, the upstream neighboring chip and the downstream neighboring chip;
• wherein the plurality of IC chips are sequentially ordered by a first set of integer indices in a first transmission direction of signals on a first bus of the plurality of buses, and wherein each IC chip is operable to selectively perform a first sequence of a combining operation and an inverting operation, or a second sequence of an inverting operation and a combining operation depending on whether an integer index of the IC chip is even or odd in the first transmission direction of signals on the first bus;
• and
• a first circuit for processing signals on a first bus of the plurality of buses, the first circuit configured to:
• receive a first input signal on the first bus from the upstream neighboring chip;
• based at least on whether the integer index of the IC chip is even or odd in the first transmission direction of signals on the first bus, perform a first sequence of a combining operation and an inverting operation, or the second sequence of an inverting operation and a combing operation, a signal produced by the IC chip and the first input signal to generate a first output signal;
• and
• transmit the first output signal to the downstream neighboring chip on the first bus.