Memory transaction queue bypass based on configurable address and bandwidth conditions
AssigneeIntel Corporation
InventorsJeffrey C. Swanson, Sreenivas Mandava, Henk Neefs, Jing Ling
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Abstract
An embodiment of an apparatus may comprise one or more substrates, and a controller coupled to the one or more substrates, the controller including circuitry to control access to a memory, convert an address for a transaction for the memory from a first address in a first address space to a second address in a second address space, determine a bandwidth bypass condition for the transaction based on a bandwidth of memory transactions for the memory, and provide the second address for the transaction to a scheduler at a time based at least in part on the determined bandwidth bypass condition. Other embodiments are disclosed and claimed.
Claims20
An electronic apparatus, comprising:
- one or more substrates;
- and
- a controller coupled to the one or more substrates, the controller comprising:
- a decoder circuit to receive a first address of a request to access a memory, wherein the first address is in a first address space, the decoder circuit further to convert first address into a second address in a second address space;
- a queue coupled to receive the second address from the decoder circuit;
- and
- a selector circuit coupled to the decoder circuit via a first path, wherein the first path bypasses the queue, the selector circuit further coupled to the queue via a second path, and further coupled to receive a control signal which is to be based on a first indication of a bandwidth of transactions which are each to access the memory, wherein, based on the control signal, the selector circuit is to select between:
- the first path to communicate the second address to a scheduler;
- and
- the second path to communicate an output of the queue to the scheduler.
An electronic system, comprising:
- memory;
- and
- a controller communicatively coupled to the memory, the controller comprising:
- a decoder circuit to receive a first address of a request to access the memory, wherein the first address is in a first address space, the decoder circuit further to convert into a second address in a second address space;
- a queue coupled to receive the second address from the decoder circuit;
- and
- a selector circuit coupled to the decoder circuit via a first path, wherein the first path bypasses the queue, the selector circuit further coupled to the queue via a second path, and further coupled to receive a control signal which is to be based on a result of an address conflict check which is performed based on the first address, wherein, based on the control signal, the selector circuit is to select between:
- the first path to communicate the second address to a scheduler;
- and
- the second path to communicate an output of the queue to the scheduler.
A method, comprising:
- receiving a first address of a request to access a memory, wherein the first address is in a first address space;
- converting the first address into a second address in a second address space;
- sending the second address to a queue;
- sending the second address to a selector circuit via a first path which bypasses the queue;
- receiving a control signal which is based on a first indication of a bandwidth of transactions which are each to access the memory;
- and
- based on the control signal, selecting between:
- the first path to communicate the second address to a scheduler;
- and
- a second path to communicate an output of the queue to the scheduler.
Dependencies are inferred from the claim text.