Accumulator for digital computation-in-memory architectures

A method for in-memory computation, comprising:

• providing, via an activation circuit, activation signals to different word-lines of a memory;
• accumulating, via each digital counter of a plurality of digital counters, output signals on a respective column of multiple columns of the memory, wherein a plurality of memory cells are on each of the multiple columns, the plurality of memory cells storing multiple bits representing weights of a neural network, wherein the plurality of memory cells of each of the multiple columns correspond to the different word-lines of the memory;
• adding, via an adder circuit, output signals of the plurality of digital counters;
• accumulating, via an accumulator, output signals of the adder circuit;
• and
• generating, via a frequency converter, a first clock signal for the activation circuit based on a second clock signal for the adder circuit.

An apparatus for in-memory computation, comprising:

• means for providing activation signals to different word-lines of a memory;
• means for counting a quantity of particular logic values of output signals on a respective column of multiple columns of a memory, wherein a plurality of memory cells are on each of the multiple columns, the plurality of memory cells being configured to store multiple bits representing weights of a neural network, wherein the plurality of memory cells of each of the multiple columns correspond to different word-lines of the memory;
• means for adding output signals of the means for counting;
• means for accumulating output signals of the means for adding;
• and
• means for generating a first clock signal for the means for providing based on a second clock signal for the means for adding.