Semiconductor device and method of manufacturing the same

A method of fabricating a semiconductor device, comprising:

• forming a plurality of first conductive patterns arranged in a first direction and embedded in a first dielectric layer and a plurality of second conductive patterns arranged in the first direction and embedded in the first dielectric layer,
• wherein the second conductive patterns are spaced-apart from the first conductive patterns along a second direction crossing the first direction, and
• the first conductive patterns are aligned along the first direction and the second conductive patterns are aligned along the first direction;
• forming a second dielectric layer over the plurality of first conductive patterns and the first dielectric layer;
• forming a plurality of openings in the second dielectric layer each over a corresponding one of the plurality of first and second conductive patterns by a first patterning operation;
• forming a blanket layer of a conductive material over the second dielectric layer and in the plurality of openings;
• patterning the blanket layer of the conductive material to form a plurality of third and fourth conductive patterns connected to a corresponding one of the plurality of first and second conductive patterns by a second patterning operation;
• and
• forming a third dielectric layer over the plurality of third and fourth conductive patterns,
• wherein in the first patterning operation, the plurality of openings as a whole are shifted in the first direction by a shift amount more than 0.1 μm from the plurality of first and second conductive patterns as a whole in plan view,
• wherein a space between the first conductive patterns and the second conductive patterns along the second direction is smaller than a space between the third conductive patterns and the fourth conductive patterns along the second direction,
• wherein a thickness of the plurality of first conductive patterns is greater than a thickness of the plurality of third conductive pattern above the second dielectric layer,
• the thickness of the plurality of first conductive patterns is in a range from 3 μm to 5 μm,
• the thickness of the plurality of third conductive patterns above the second dielectric layer is in a range from 1.0 μm to 3.0 μm,
• wherein a center line between the plurality of third conductive patterns and fourth conductive patterns extending in the first direction overlaps the plurality of first or second conductive patterns in plan view, and
• a center line between adjacent third conductive patterns and adjacent fourth conductive patterns extending in the second direction overlaps first and second conductive patterns in plan view.

A method of fabricating a semiconductor device having patterns, wherein the patterns include conductive patterns and island patterns, comprising:

• forming lower conductive patterns arranged in a column-row matrix over a substrate, a first space between adjacent rows of the lower conductive patterns being in a range from 0.8 μm to 1.2 μm;
• forming a first dielectric layer over the lower conductive patterns;
• forming upper conductive patterns over the lower conductive patterns, the upper conductive patterns being arranged in a column-row matrix, a second space between adjacent rows of the upper conductive patterns being greater than the first space;
• forming a first island pattern at a same level as the lower conductive patterns spaced apart from a closest pattern at the same level as the lower conductive patterns by a distance two to ten times greater than a pitch of the lower conductive patterns' column-row matrix;
• forming a second island pattern at a same level as the upper conductive patterns spaced apart from a closest pattern at the same level as the upper conductive patterns by a distance two to ten times greater than a pitch of the upper conductive patterns' column-row matrix;
• and
• forming a passivation layer over the first island pattern and the second island pattern, wherein:
• a center line of adjacent rows of the lower conductive patterns is shifted in a row direction by a shift amount more than 0.1 μm from a center line of adjacent two rows of the upper conductive patterns, and
• a center of the first island pattern is aligned with a center of the second island pattern along a direction extending away from the substrate.