Integrated circuit packages to minimize stress on a semiconductor die

An apparatus to reduce stress between an integrated circuit (IC) package and a semiconductor die included in the apparatus, the apparatus comprising:

• a printed circuit board coupled to the IC package, the IC package housing the semiconductor die;
• and
• wherein the IC package includes:
• an IC package substrate;
• a dielectric material or a polymeric material disposed on the semiconductor die;
• and
• an adhesive layer coupling the semiconductor die to the IC package substrate, the adhesive layer having a modulus of elasticity of no greater than about 3 gigapascals (GPa).