Semiconductor package including a barrier structure covering connection pads and contacting a protruding portion of an adhesive layer

A semiconductor package, comprising:

• a first semiconductor chip including a first device layer, wherein the first device layer includes a first interlayer insulating layer, a first interconnection structure, and first connection pads;
• a second semiconductor chip having a lower surface facing the first device layer of the first semiconductor chip and including second connection pads;
• connection bumps disposed between the first semiconductor chip and the second semiconductor chip and electrically connecting the first connection pads and the second connection pads to each other;
• an adhesive layer interposed between the first semiconductor chip and the second semiconductor chip, the adhesive layer at least partially surrounding the connection bumps, and contacting the first device layer;
• and
• a barrier structure contacting the first device layer and the adhesive layer, spaced apart from the connection bumps, and at least partially surrounding regions in which the connection bumps are disposed,
• wherein the barrier structure is spaced apart from the regions in which the connection bumps are disposed.

A semiconductor package, comprising:

• a first semiconductor chip including a first semiconductor layer, a through-via passing through the first semiconductor layer, a first interconnection structure, and first connection pads disposed on an upper surface of the first semiconductor layer and electrically connected to the through-via;
• a second semiconductor chip disposed on the first semiconductor chip and including a second semiconductor layer, a second interconnection structure, and second connection pads;
• connection bumps contacting the first connection pads and the second connection pads between the first semiconductor chip and the second semiconductor chip;
• an adhesive layer interposed between the first semiconductor chip and the second semiconductor chip and at least partially surrounding the connection bumps, the adhesive layer including a protruding portion protruding from a side surface of the second semiconductor chip in an outward direction away from the side surface of the second semiconductor chip;
• a barrier structure disposed between one of the first connection pads and the protruding portion of the adhesive layer, and including an overlapping region vertically overlapping the second semiconductor chip and a non-overlapping region that does not vertically overlap the second semiconductor chip;
• and
• an encapsulant at least partially covering the barrier structure, the protruding portion of the adhesive layer, and the second semiconductor chip on the first semiconductor chip,
• wherein the non-overlapping region of the barrier structure extends in the outward direction, with respect to the protruding portion of the adhesive layer,
• wherein the barrier structure is spaced apart from another one of the first connection pads that is immediately next to the one of the first connection pads.