Sequencing chip and manufacturing method therefor

A chip matrix, comprising:

• a wafer, wherein the wafer has cutting lines that are evenly distributed on the wafer;
• a first silicon oxide layer, wherein the first silicon oxide layer is made of silicon oxide and is formed on an upper surface of the wafer;
• a transition metal oxide layer, wherein the transition metal oxide layer is made of a transition metal oxide and is formed on an upper surface of the first silicon oxide layer;
• and
• a second silicon oxide layer, wherein the transition metal oxide layer is of a continuous layer structure, and the second silicon oxide layer is made of silicon oxide and formed on an upper surface of the transition metal oxide layer as a plurality of wells that are connected to each other;
• or wherein the transition metal oxide layer consists of a plurality of transition metal oxide spots that are unconnected to each other, and the second silicon oxide layer is formed on the upper surface of the first silicon oxide layer located among the plurality of transition metal oxide spots that are unconnected to each other,
• wherein the wafer is a quartz wafer, the second silicon oxide layer has a thickness ranging from 100 nm to 200 nm.