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US 12,538,570 B2Granted
Reduction of gate-drain capacitance
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsJung-Hung Chang, Lo-Heng Chang, Zhi-Chang Lin, Shih-Cheng Chen, Kuo-Cheng Chiang, Chih-Hao Wang
Life of this patent
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Abstract
A semiconductor device according to the present disclosure includes a bottom dielectric feature on a substrate, a plurality of channel members directly over the bottom dielectric feature, a gate structure wrapping around each of the plurality of channel members, two first epitaxial features sandwiching the bottom dielectric feature along a first direction, and two second epitaxial features sandwiching the plurality of channel members along the first direction.
Claims20
A method, comprising:
- receiving a workpiece comprising:
- a bottom sacrificial layer on a substrate,
- a bottom capping layer on the bottom sacrificial layer, and
- a stack on the bottom capping layer, the stack comprising a plurality of channel layers interleaved by a plurality of sacrificial layers;
- patterning the stack and a portion of the substrate to form a fin-shaped structure having a channel region and a source/drain region;
- forming a dummy gate stack over the channel region;
- recessing the source/drain region to form a source/drain trench that exposes sidewalls of the bottom sacrificial layer, sidewalls of the bottom capping layer, sidewalls of the plurality of channel layers, and sidewalls of the plurality of sacrificial layers;
- selectively and partially recessing the sidewalls of the plurality of sacrificial layers to form inner spacer recesses;
- forming inner spacer features in the inner spacer recesses;
- after the forming of the inner spacer features, selectively removing the bottom sacrificial layer to form a bottom vacancy;
- forming a bottom dielectric layer in the bottom vacancy;
- depositing a dielectric liner over sidewalls of the dummy gate stack, sidewalls of the inner spacer features, and sidewalls of the bottom dielectric layer;
- forming a first epitaxial layer over the source/drain region;
- selectively removing the dielectric liner not covered by the first epitaxial layer;
- after the selectively removing, depositing a second epitaxial layer over the dielectric liner and the first epitaxial layer;
- removing the dummy gate stack;
- selectively removing the plurality of sacrificial layers in the channel region to release the plurality of channel layers as channel members;
- and
- forming a gate structure to wrap around each of the channel members.
16 more elements
A method, comprising:
- receiving a workpiece comprising:
- a bottom sacrificial layer on a substrate,
- a bottom capping layer on the bottom sacrificial layer, and
- a stack on the bottom capping layer, the stack comprising a plurality of channel layers interleaved by a plurality of sacrificial layers;
- patterning the stack and a portion of the substrate to form a fin-shaped structure having a channel region and a source/drain region;
- forming a dummy gate stack over the channel region;
- recessing the source/drain region to form a source/drain trench that exposes sidewalls of the bottom sacrificial layer, sidewalls of the bottom capping layer, sidewalls of the plurality of channel layers, and sidewalls of the plurality of sacrificial layers;
- selectively and partially recessing the sidewalls of the plurality of sacrificial layers to form inner spacer recesses;
- forming inner spacer features in the inner spacer recesses;
- after the forming of the inner spacer features, oxidizing the bottom sacrificial layer to form a bottom dielectric layer between the bottom capping layer and the substrate;
- depositing a dielectric liner over sidewalls of the dummy gate stack, sidewalls of the inner spacer features, and sidewalls of the bottom dielectric layer;
- forming a first epitaxial layer over the source/drain region;
- selectively removing the dielectric liner not covered by the first epitaxial layer;
- after the selectively removing, depositing a second epitaxial layer over the dielectric liner and the first epitaxial layer;
- removing the dummy gate stack;
- selectively removing the plurality of sacrificial layers in the channel region to release the plurality of channel layers as channel members;
- and
- forming a gate structure to wrap around each of the channel members.
15 more elements
A method, comprising:
- depositing a bottom sacrificial layer on a substrate;
- depositing a bottom capping layer on the bottom sacrificial layer;
- depositing, on the bottom capping layer, a stack formed of a plurality of channel layers interleaved by a plurality of sacrificial layers;
- forming a fin-shaped structure out of the substrate, the bottom sacrificial layer, the bottom capping layer, and the stack;
- forming a dummy gate stack over a channel region of the fin-shaped structure;
- forming a spacer layer over the dummy gate stack;
- recessing a source/drain region of the fin-shaped structure to expose sidewalls of the bottom sacrificial layer, the bottom capping layer, and the stack;
- selectively and partially recessing the plurality of sacrificial layers to form inner spacer recesses;
- forming inner spacer features in the inner spacer recesses;
- and
- after the forming of the inner spacer features, replacing the bottom sacrificial layer with a bottom dielectric feature.
8 more elements
Dependencies are inferred from the claim text.