Memory device implementing unified memory architecture integrating multiple memory types

A semiconductor memory device, comprising:

• a semiconductor substrate comprising a first memory region, a second memory region and a logic region;
• a flash memory array formed in the first memory region and comprising an array of magnetoresistive random-access (MRAM) memory cells, each MRAM memory cell including an access transistor coupled to a magnetic tunnel junction (MTJ) storage element;
• a read-only memory (ROM) array formed in the second memory region, the read-only memory array comprising an array of read-only (ROM) memory cells, each ROM memory cell including an access transistor coupled to a short or open circuit as the ROM storage element;
• a memory peripheral circuit formed in the logic region, the memory peripheral circuit including control circuits for receiving input commands and executing memory operations to the memory cells in the flash memory array and the ROM array;
• a plurality of metal layers formed on the semiconductor substrate, each metal layer being isolated from an adjacent metal layer by an interlayer dielectric layer,
• wherein the MTJ storage element of each MRAM memory cell is formed in a via opening formed in the interlayer dielectric layer between a first one of the metal layers and a second one of the metal layers;
• and
• wherein the ROM storage element of each ROM memory cell is formed in the interlayer dielectric layer between the first one of the metal layers and the second one of the metal layers as a conductive via or the absence of a conductive via, the conductive via forming a short circuit ROM storage element and the absence of a conductive via forming an open circuit ROM storage element.