Memory device having electrically floating body transistor

A semiconductor memory array comprising:

• a plurality of semiconductor memory cells arranged in a matrix of rows and columns, wherein each said semiconductor memory cell includes:
• a first bipolar device having a first floating base region, a first collector, and a first emitter, and a second bipolar device having a second floating base region, a second collector, and a second emitter;
• wherein said first floating base region is common to said second floating base region;
• wherein said first collector is common to said second collector;
• and a transistor comprising said first emitter, said first floating base region, and said second emitter, wherein at least one of said first bipolar device or second bipolar device maintains a state of said semiconductor memory cell;
• wherein current flow through said transistor during a read operation is determined by said state of said semiconductor memory cell;
• wherein said first and second collectors are commonly connected to at least two of said semiconductor memory cells;
• and wherein said first and second collectors have a band gap that is lower than a band gap of said first and second floating base regions.

An integrated circuit comprising:

• a semiconductor memory array comprising:
• a plurality of semiconductor memory cells arranged in a matrix of rows and columns, wherein each said semiconductor memory cell includes:
• a first bipolar device having a first floating base region, a first collector, and a first emitter;
• and a second bipolar device having a second floating base region, a second collector, and a second emitter;
• wherein said first floating base region is common to said second floating base region;
• wherein said first collector is common to said second collector;
• and a transistor comprising said first emitter, said first floating base region, and said second emitter, wherein at least one of said first bipolar device or second bipolar device maintains a state of said semiconductor memory cell;
• wherein current flow through said transistor during a read operation is determined by said state of said semiconductor memory cell;
• wherein said first and second collectors are commonly connected to at least two of said semiconductor memory cells;
• wherein said first and second collectors have a band gap that is lower than a band gap of said first and second floating base regions;
• and a control circuit configured to provide electrical signals to control application of back bias to at least two of said plurality of semiconductor memory cells.