US 12,537,663 B2 · Programmable delay-locked loop (DLL) that utilizes a low power phase detector

Abstract

A delay-locked loop (DLL) is provided that ensures that the phase outputs that are provided as inputs to the harmonic rejection mixer (HRM) are sufficiently accurate to allow the HRM to effectively cancel out the spurious harmonic frequencies, thereby improving HRM parameters. The phase detector of the DLL can be programmable to provide a “knob” that can be used post layout to adjust the output phase differences of the DLL to make them more precise. This feature overcomes issues with mismatches in silicon that in the past have affected the ability of the DLL to settle precisely to the desired phases. This, in turn, loosens design and manufacturing constraints that are currently employed to ensure that the DLLs settle precisely to the desired phases. Additionally, logic gates are eliminated from the phase detector and replaced with resistors to reduce current consumption and further looser design and manufacturing constraints.

Claims20

Dependent claims

An apparatus comprising:

a phase detector (PD) comprising:
an input stage configured to receive a plurality of quadrature phases and a plurality of 45° phases having a second duty cycle from a duty cycle converter (DTC) of a delay-locked loop (DLL) that converts a plurality of quadrature phases and a plurality of 45° phases having a first duty cycle into the plurality of quadrature phases and the plurality of 45° phases having the second duty cycle;
and
at least first and second sets of resistors electrically coupled to the input stage for receiving the plurality of quadrature phases and the plurality of 45° phases having the second duty cycle, respectively, wherein the resistors of the first set of resistors sum the plurality of quadrature phases received in the input stage together to generate a first PD output voltage signal and wherein the resistors of the second set of resistors sum the plurality of 45° phases received at the input stage together to generate a second PD output voltage signal, the first and second PD output voltage signals being output from first and second output terminals of the PD, respectively.

1 more element

A radio frequency (RF) transceiver comprising:

a delay-locked loop (DLL) comprising:
a plurality of differential delay lines, each differential delay line being configured to input a first clock signal and to output a quadrature phase and a 45° phase, the quadrature phase and 45° phase having a first duty cycle, the differential delay lines comprising control circuits configured to control delays of delay elements of the differential delay lines;
a duty cycle converter (DTC) configured to input the quadrature phase and 45° phase having the first duty cycle and to output quadrature phases and 45° phases having a second duty cycle;
and
a phase detector (PD) comprising:
an input stage configured to receive the quadrature phases and 45° phases having the second duty cycle that are output from the DTC;
and
at least first and second sets of resistors electrically coupled to the input stage for receiving the quadrature phases and the 45° phases having the second duty cycle, respectively, from the input stage, wherein the resistors of the first set of resistors sum the quadrature phases received in the input stage together to generate a first PD output voltage signal and wherein the resistors of the second set of resistors sum the 45° phases received at the input stage together to generate a second PD output voltage signal, the first and second PD output voltage signals being output from first and second output terminals of the PD, respectively.

5 more elements

Dependencies are inferred from the claim text.

Programmable delay-locked loop (DLL) that utilizes a low power phase detector

Life of this patent

Programmable delay-locked loop (DLL) that utilizes a low power phase detector

Life of this patent

Abstract

Claims20