Error correction code (ECC) circuit including low-density parity-check decoder in adaptive operation mode, operating method of the ECC circuit, and memory controller including the ECC circuit

An error correction code (ECC) circuit comprising:

• a low-density parity-check (LDPC) encoder configured to encode write data received from a host;
• and
• an LDPC decoder configured to
• receive a codeword from a memory device, wherein the codeword corresponds to data read from the memory device in response to receiving a read request from the host,
• calculate a syndrome vector based on the codeword and a parity-check matrix, the parity-check matrix including information indicating that a plurality of messages are exchanged between a plurality of check nodes and a plurality of variable nodes,
• perform, based on the syndrome vector being not a zero vector, sequential decoding on a plurality of columns of the parity-check matrix by variably setting an operation mode for decoding each column of the plurality of columns, wherein the operation mode is set from a plurality of operation mode including a first operation mode, a second operation mode, and a third operation mode, and performing the sequential decoding on the plurality of columns comprises
• decoding a first column in the first operation mode,
• decoding a second column in the second operation mode, and
• decoding a third column in the third operation mode,
• calculate the syndrome vector based on the sequential decoding of the plurality of columns being completed,
• iteratively perform the sequential decoding until the syndrome vector is the zero vector to obtain decoded data;
• and
• transmit the decoded data to the host.

An operating method of an error correction code (ECC) circuit, the operating method comprising:

• receiving, by the ECC circuit, a codeword from a memory device, wherein the codeword corresponds to data read from the memory device in response to receiving a read request from a host;
• obtaining, by the ECC circuit, an error metric with respect to each column of a plurality of columns of a parity-check matrix by performing a first decoding iteration on the codeword;
• determining, by the ECC circuit, one operation mode of a first operation mode, a second operation mode, and a third operation mode to be an operation mode for each column of the plurality of columns based on the error metric obtained in the first decoding iteration and a variable node degree of each column of the plurality of columns;
• performing, by the ECC circuit, a second decoding iteration according to the operation mode determined for each column of the plurality of columns to obtain decoded data;
• and
• transmitting, by the ECC circuit, the decoded data to the host.