Charge injection reduction in a fractional-N frequency synthesizer
AssigneeSilicon Laboratories Inc.
InventorsYun Da Bryan Seah, Hua Beng Chan, Tak Ying Wong
Life of this patent
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Abstract
A technique for reducing the effects of charge injection when a charge pump in a fractional-N frequency synthesizer switches from an error cancellation phase of error current generation to a full-scale phase of error current generation uses a dummy digital-to-analog converter to steer excess current from the error cancellation phase to a voltage regulated node. As a result, the voltage swing of an inactive branch of a digital-to-analog converter of the charge pump is the same as the voltage swing of the active branch of the charge pump, i.e., the device overlap capacitance charge injection is in phase for the branches of a digital-to-analog converter in the charge pump.
Claims20
A method for fractional-N frequency synthesis, the method comprising:
- providing an error current to a loop filter based on a selection code, an error cancellation phase of error current generation, a full-scale phase of the error current generation, and an opposing full-scale phase of the error current generation;
- and
- steering excess current to a voltage-regulated node based on the selection code, the excess current being generated by switching from the error cancellation phase of the error current generation to the full-scale phase of the error current generation.
A fractional-N frequency synthesizer comprising:
- a digital-to-analog converter configured to provide an error current to a loop filter based on a selection code, an error cancellation phase control signal, a full-scale phase control signal, and an opposing full-scale phase control signal;
- and
- a dummy digital-to-analog converter configured to steer excess current to a voltage-regulated node based on the selection code, the error cancellation phase control signal, the full-scale phase control signal, and the opposing full-scale phase control signal.
An apparatus comprising:
- means for providing an error current to a loop filter of a phase-locked loop, the error current being provided to the loop filter based on a selection code, an error cancellation phase of error current generation, a full-scale phase of the error current generation, and an opposing full-scale phase of the error current generation;
- and
- means for steering excess current to a voltage-regulated node based on the selection code, the excess current being generated by switching from the error cancellation phase of the error current generation to the full-scale phase of the error current generation.
Dependencies are inferred from the claim text.