Phase adjustment circuit

A phase adjustment circuit comprising:

• a clock generation unit configured to generate a sinusoidal differential clock signal;
• a first variable amplifier configured to receive the differential clock signal, adjust an amplitude of the differential clock signal based on a first gain control signal, and output an amplitude-adjusted differential clock signal;
• a second variable amplifier configured to receive the differential clock signal, adjust an amplitude of the differential clock signal based on a second gain control signal to generate an amplitude-adjusted in-phase signal, and output the amplitude-adjusted in-phase signal;
• an adding unit including:
• a first adding circuit configured to add a positive phase side of the amplitude-adjusted differential clock signal and the amplitude-adjusted in-phase signal to generate a first sum signal, and
• a second adding circuit configured to add a negative phase side of the amplitude-adjusted differential clock signal and the amplitude-adjusted in-phase signal to generate a second sum signal;
• a differential transmission line including a first transmission line configured to receive the first sum signal and a second transmission line configured to receive the second sum signal, the first and second transmission lines being electromagnetically coupled to each other and having different propagation speeds for differential mode and common mode signals;
• and
• a terminal circuit connected to a first end of the first transmission line and a first end of the second transmission line;
• wherein a phase-adjusted sinusoidal signal is output from the first end of the first transmission line or the first end of the second transmission line.