Memory device

A memory device comprising:

• a memory control unit comprising an input/output unit, a control unit, and a first management unit;
• and
• a memory unit comprising a plurality of memory blocks,
• wherein the first management unit comprises a plurality of first memory elements,
• wherein the control unit is configured to convert an address input through the input/output unit to an address of the memory block corresponding to the address, with use of a first management table retained in the plurality of first memory elements, and
• wherein each of the plurality of first memory elements comprises a first transistor, a second transistor, and a first capacitor,
• wherein the first capacitor comprises a ferroelectric layer,
• wherein one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor and to one electrode of the first capacitor, and
• wherein the first transistor has a back gate, and the second transistor does not have a back gate.