Semiconductor circuit, driving method, and electronic apparatus

A driving method comprising:

• performing a first driving operation on a semiconductor circuit, the semiconductor circuit including a first inverter, a second inverter, a first control line, a first storage circuit, a first power supply switch, a second power supply switch, a first bit line and a second bit line, a first word line, a first transistor, and a second transistor, the first inverter that is coupled to a first power supply node and a second power supply node, is configured to generate an inverted voltage of a voltage at a first node, and is configured to apply the inverted voltage of the voltage at the first node to a second node, the second inverter that is coupled to the first power supply node and the second power supply node, is configured to generate an inverted voltage of a voltage at the second node, and is configured to apply the inverted voltage of the voltage at the second node to the first node, the first storage circuit including a first storage element provided on a first path coupling the first node and the first control line, and a second storage element provided on a second path coupling the second node and the first control line, the first power supply switch that is configured to supply a first power supply voltage to the first power supply node by being turned on, the second power supply switch that is configured to supply a second power supply voltage to the second power supply node by being turned on, the first transistor that has a gate coupled to the first word line, and is configured to couple the first bit line and the first node by being turned on, the second transistor that has a gate coupled to the first word line, and is configured to couple the second bit line and the second node by being turned on, the first driving operation in which, in a period in which the first power supply switch and the second power supply switch are turned on, the first word line is set active, and signals having logic levels different from each other are applied to the respective first bit line and second bit line;
• and
• performing a second driving operation in which, in a period in which the first power supply switch and the second power supply switch are turned off, the first word line is set active, and a first alternating-current signal and a second alternating-current signal are respectively applied to the first bit line and the second bit line, and the first alternating-current signal and the second alternating-current signal being signals in phase with each other.

An electronic apparatus provided with a semiconductor circuit, the semiconductor circuit comprising:

• a first inverter that is coupled to a first power supply node and a second power supply node, is configured to generate an inverted voltage of a voltage at a first node, and is configured to apply the inverted voltage of the voltage at the first node to a second node;
• a second inverter that is coupled to the first power supply node and the second power supply node, is configured to generate an inverted voltage of a voltage at the second node, and is configured to apply the inverted voltage of the voltage at the second node to the first node;
• a first control line;
• a first storage circuit including a first storage element and a second storage element, the first storage element provided on a first path coupling the first node and the first control line, and the second storage element provided on a second path coupling the second node and the first control line;
• a first power supply switch that is configured to supply a first power supply voltage to the first power supply node by being turned on;
• a second power supply switch that is configured to supply a second power supply voltage to the second power supply node by being turned on;
• a first bit line and a second bit line;
• a first word line;
• a first transistor that has a gate coupled to the first word line, and is configured to couple the first bit line and the first node by being turned on;
• a second transistor that has a gate coupled to the first word line, and is configured to couple the second bit line and the second node by being turned on;
• and
• a driving section that is configured to perform a first driving operation and a second driving operation, the first driving operation in which, in a period in which the first power supply switch and the second power supply switch are turned on, the first word line is set active, and signals having logic levels different from each other are applied to the respective first bit line and second bit line, the second driving operation in which, in a period in which the first power supply switch and the second power supply switch are turned off, the first word line is set active, and a first alternating-current signal and a second alternating-current signal are respectively applied to the first bit line and the second bit line, and the first alternating-current signal and the second alternating-current signal being signals in phase with each other.