Apparatus for page-copy data accessing

An apparatus for page-copy data accessing, comprising:

• a memory cell array, divided into a plurality of memory sections, each memory section comprising a plurality of memory cells which are partitioned into multiple pages and each page of memory cells is coupled by a corresponding word line,
• a plurality of bit-line sense-amplifier/buffers (BLSABFs), coupled to the memory cell array through a plurality of bit-lines or bit-line pairs, each BLSABF being coupled to two bit-lines or bit-line pairs located in the two different memory sections on opposite sides of the BLSABF, data voltage signals on the bit-lines or bit-line pairs in a memory section, by the signal sensing and buffering performed by the plurality of BLSABFs, are transferred to the bit-lines or bit-line pairs in an adjacent memory section adjacent to the memory section, the voltage data signals are sequentially propagated across
• a plurality of subsequent memory sections through a plurality of BLSABFs, which are coupled to two adjacent memory sections of the subsequent memory sections, wherein each of the plurality of BLSABFs comprises:
• a propagating control circuit, coupled to a bit-line or bit-line pair in the memory section and a bit-line or bit-line pair in the adjacent memory section adjacent to the memory section, configured to transfer a data voltage signal in the memory section/adjacent memory section to a bit-line or bit-line pair in the adjacent memory section/memory section in response to a propagating control signal;
• and
• a latch circuit, coupled to the bit-line or bit-line pair in the memory section and the adjacent memory section, and configured to sense the data voltage signal and latch the sensed/amplified data voltage signal in response to a sensing or latch control signal;
• a plurality of page buffers, coupled to all of or part of the plurality of BLSABFs, and configured to receive the data voltage signals from the coupled BLSABFs to a data interface of the apparatus, or configured to store data voltage signals from the data interface of the apparatus to the coupled BLSABFs;
• and
• a logic operation processing circuit, coupled to the plurality of page buffers and configured to receive the data voltage signals from the plurality of page buffers and perform a bit-wise multiplication operation on the data voltage signals.