RC-tuned wordline underdrive circuit

A method comprising:

• storing data in an array of memory bit cells arranged as a plurality of rows and a plurality of columns, each configured to store data;
• generating, by each of a plurality of word line driver circuits, a corresponding word line for the plurality of rows of the array of memory bit cells;
• and
• adjusting, via a configurable resistor-capacitor circuit of an underdrive circuit coupled to the plurality of word line driver circuits, a rate of change in a voltage level of a given word line generated by a given word line driver circuit of the plurality of word line driver circuits.

A computing system comprising:

• a memory comprising:
• an array of memory bit cells arranged as a plurality of rows and a plurality of columns, each configured to store data;
• and
• a plurality of word line driver circuits, each configured to generate a corresponding word line for the plurality of rows of the array of memory bit cells;
• and
• an underdrive circuit coupled to the plurality of word line driver circuits configured to adjust, via a configurable resistor-capacitor circuit, a rate of change in a voltage level of a given word line generated by a given word line driver circuit of the plurality of word line driver circuits;
• and
• a processor configured to generate memory access requests targeting data stored in the memory.