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US 12,536,970 B2Granted
Display device
AssigneeSemiconductor Energy Laboratory Co., Ltd.
InventorsHidetomo Kobayashi, Kei Takahashi, Shunpei Yamazaki
Life of this patent
Estimating the term…
Abstract
A display device with favorable display quality is provided. A display portion where a plurality of pixels is arranged in a matrix is divided into Region A and Region B, i.e., regions on the upstream side and the downstream side of a scanning direction. A signal line for supplying an image signal is provided in each of Region A and Region B. Region A and Region B adjoin each other such that a boundary line showing the boundary between the regions is bent. Bending the boundary line suppresses formation of a stripe in a boundary portion. For example, in a given column, the total number of pixels electrically connected to a signal line in Region A is made different from the total number of pixels electrically connected to a signal line in Region B.
Claims3
A display device comprising:
- a display panel, the display panel comprising:
- a first scan line driver circuit over a substrate;
- a second scan line driver circuit over the substrate;
- a signal line driver circuit;
- a demultiplexer;
- and
- a pixel portion comprising a plurality of pixels,
- wherein one of the plurality of pixels comprises:
- a first transistor;
- a second transistor;
- a third transistor;
- a capacitor;
- and
- a display element,
- wherein the first transistor comprises:
- a first electrode over the substrate, the first electrode being configured to function as a back gate electrode of the first transistor;
- a first insulating layer over the first electrode, the first insulating layer comprising a stack of layers;
- a semiconductor layer over the first insulating layer, the semiconductor layer comprising a metal oxide;
- a second insulating layer over the semiconductor layer;
- a second electrode over the second insulating layer, the second electrode being configured to function as a gate electrode of the first transistor;
- a third insulating layer over the second electrode;
- a third electrode over the third insulating layer, the third electrode being configured to function as one of a source electrode and a drain electrode of the first transistor;
- and
- a fourth electrode over the third insulating layer, the fourth electrode being configured to function as the other of the source electrode and the drain electrode of the first transistor,
- wherein each of the third electrode and the fourth electrode is electrically connected to the semiconductor layer via an opening provided in the third insulating layer,
- wherein the second insulating layer extends beyond an end portion of the second electrode of the first transistor,
- wherein the third insulating layer is in contact with a side surface of the second insulating layer,
- wherein the gate electrode of the first transistor is electrically connected to a gate electrode of the third transistor and a second wiring,
- wherein the one of the source electrode and the drain electrode of the first transistor is electrically connected to a first wiring,
- wherein the other of the source electrode and the drain electrode of the first transistor is electrically connected to a gate electrode of the second transistor and a first electrode of the capacitor,
- wherein one of a source electrode and a drain electrode of the third transistor is electrically connected to a third wiring,
- wherein the other of the source electrode and the drain electrode of the third transistor is electrically connected to a second electrode of the capacitor, one of a source electrode and a drain electrode of the second transistor, and a first electrode of the display element,
- wherein the pixel portion is provided between the first scan line driver circuit and the second scan line driver circuit,
- wherein one of the first scan line driver circuit and the second scan line driver circuit is electrically connected to the second wiring,
- wherein the signal line driver circuit is electrically connected to the pixel portion,
- wherein each of the first scan line driver circuit and the second scan line driver circuit comprises a transistor comprising polycrystalline silicon in a channel formation region, and
- wherein the demultiplexer is electrically connected to an output terminal of the signal line driver circuit.
34 more elements
A display device comprising:
- a display panel, the display panel comprising:
- a first scan line driver circuit over a substrate;
- a second scan line driver circuit over the substrate;
- a signal line driver circuit;
- a demultiplexer;
- and
- a pixel portion comprising a plurality of pixels,
- wherein one of the plurality of pixels comprises:
- a first transistor;
- a second transistor;
- a third transistor;
- a capacitor;
- and
- a display element,
- wherein the first transistor comprises:
- a first electrode over the substrate, the first electrode being configured to function as a back gate electrode of the first transistor;
- a first insulating layer over the first electrode, the first insulating layer comprising a stack of layers;
- a semiconductor layer over the first insulating layer, the semiconductor layer comprising a metal oxide;
- a second insulating layer over the semiconductor layer;
- a second electrode over the second insulating layer, the second electrode being configured to function as a gate electrode of the first transistor;
- a third insulating layer over the second electrode;
- a third electrode over the third insulating layer, the third electrode being configured to function as one of a source electrode and a drain electrode of the first transistor;
- and
- a fourth electrode over the third insulating layer, the fourth electrode being configured to function as the other of the source electrode and the drain electrode of the first transistor,
- wherein each of the third electrode and the fourth electrode is electrically connected to the semiconductor layer via an opening provided in the third insulating layer,
- wherein the gate electrode of the first transistor is electrically connected to a gate electrode of the third transistor and a first wiring,
- wherein one of a source electrode and a drain electrode of the first transistor is electrically connected to a gate electrode of the second transistor and a first electrode of the capacitor,
- wherein one of a source electrode and a drain electrode of the third transistor is electrically connected to a second electrode of the capacitor, one of a source electrode and a drain electrode of the second transistor, and a first electrode of the display element,
- wherein the pixel portion is provided between the first scan line driver circuit and the second scan line driver circuit,
- wherein one of the first scan line driver circuit and the second scan line driver circuit is electrically connected to the first wiring,
- wherein the signal line driver circuit is electrically connected to the pixel portion,
- wherein each of the first scan line driver circuit and the second scan line driver circuit comprises a transistor comprising polycrystalline silicon in a channel formation region,
- wherein the demultiplexer is electrically connected to an output terminal of the signal line driver circuit, and
- wherein a potential applied to the gate electrode of the first transistor and the back gate electrode of the first transistor is the same.
31 more elements
A display device comprising:
- a display panel, the display panel comprising:
- a first scan line driver circuit over a substrate;
- a second scan line driver circuit over the substrate;
- a signal line driver circuit;
- a demultiplexer;
- and
- a pixel portion comprising a plurality of pixels,
- wherein one of the plurality of pixels comprises:
- a first transistor;
- a capacitor;
- and
- a display element,
- wherein the first transistor comprises:
- a first electrode over the substrate, the first electrode being configured to function as a back gate electrode of the first transistor;
- a first insulating layer over the first electrode, the first insulating layer comprising a stack of layers;
- a semiconductor layer over the first insulating layer, the semiconductor layer comprising a metal oxide;
- a second insulating layer over the semiconductor layer;
- a second electrode over the second insulating layer, the second electrode being configured to function as a gate electrode of the first transistor;
- a third insulating layer over the second electrode;
- a third electrode over the third insulating layer, the third electrode being configured to function as one of a source electrode and a drain electrode of the first transistor;
- and
- a fourth electrode over the third insulating layer, the fourth electrode being configured to function as the other of the source electrode and the drain electrode of the first transistor,
- wherein each of the third electrode and the fourth electrode is electrically connected to the semiconductor layer via an opening provided in the third insulating layer,
- wherein the second insulating layer extends beyond an end portion of the second electrode of the first transistor,
- wherein the third insulating layer is in contact with a side surface of the second insulating layer,
- wherein the pixel portion is provided between the first scan line driver circuit and the second scan line driver circuit,
- wherein one of the first scan line driver circuit and the second scan line driver circuit is electrically connected to the second electrode of the first transistor,
- wherein the signal line driver circuit is electrically connected to the pixel portion,
- wherein each of the first scan line driver circuit and the second scan line driver circuit comprises a transistor comprising polycrystalline silicon in a channel formation region,
- wherein the demultiplexer is electrically connected to an output terminal of the signal line driver circuit, and
- wherein the one of the plurality of pixels has an aperture ratio of up to 45.6%.
28 more elements
Dependencies are inferred from the claim text.